Design Simulation Systems Ltd
Dsim is a high-level, event-driven digital circuit simulator. Most of the outline code was written in Liang Kee's restaurant, in Singapore, during a particularly productive lunch hour.
Digital simulators only need to have an understanding of minimal circuit elements known as 'primitives' which contain the logic code of each primitive function.Simulators which haven't had a lot of thought put into their design, use the logic gate as the primitive. and break down each circuit into the equivalent gate-level representation.
This means that, before a circuit can be simulated, it must be broken down into an equivalent representation, which may comprise thousands of gates. Additionally, during the simulation, each gate will have to be evaluated, at each event step, leading to a heavy computing overhead. Dsim doesn't do this. It understands high level primitives, and simulates a circuit at their level. This means that the netlist compiler, which converts the graphical circuit representation into a netlist, can be very fast and memory efficient, since it only has to flatten the circuit hierarchy to reduce the circuit to the primitive level. Having high-level primitives such as these also makes for very efficient simulation since, at each time-step, only one primitive needs to be evaluated per logic function, not a bunch of gates.
Non-inverting Tristate buffer with positive enable
Non-inverting Tristate buffer with negative enable
Inverting Tristate buffer with positive enable
Inverting Tristate buffer with negative enable
Multiple-input AND gate
Multiple-input NAND gate
Multiple-input OR gate
Multiple-input NOR gate
Two-input Exclusive-OR gate
Two-input Exclusive-NOR gate
Transparent R-S Latch
Edge-triggered R-S Latch
Memory (RAM or ROM)
Multiple-input Full Adder
Dsim's digital circuit schematics are created in GEX, in exactly the same way as analogue schematics, with the exception that they use devices from the 'DIGITAL' menu. This schematic is a D-type flipflop, done the hard way. I've only included it because the path through the logic is a tortuous one, and the events are complicated by multiple feedback paths.
The netlist is generated by the digital netlist compiler, GTL, and looks like this:
DTYPE Rev Nodes .sim 1 360 0 .print sim v(1) v(2) v(3) v(4) v(5) v(6) v(7) v(8) v(9) v(10) v(11) v(12) v(13) !C 4 0 75 150 !P 1 1 50 200 U11 11 12 13 NAND2 20 U10 10 13 12 NAND2 20 U9 9 3 11 NAND2 20 U8 8 3 10 NAND2 20 U7 7 8 9 NAND2 20 U6 6 9 8 NAND2 20 U5 2 3 7 NAND2 20 U4 1 3 6 NAND2 20 U3 4 5 3 XNOR 30 U2 4 5 INV 40 U1 1 2 INV 15It's fairly self-explanatory, if you understand SPICE netlists, except, perhaps for the !C line, which is the clock, and the !P line, which is the 'D' input signal description.
Dsim is then started by its graphical interface, 'vlogic', and runs the simulation, the results of which are shown below. The top two waveforms are the clock input and the 'CLEAR' inputs, respectively, and the tick marks on each waveform are the event markers.
Linux 64-bit Downloads
vlogic digital simulator graphical interface
GTL digital simulator netlist generator
Memory, counter and shift register primitives may not work
I haven't checked this, but I seem to remember that these were broken when RCS lost the version in which they were implemented. I'll fix them soon...
Setup and hold violations are not treated correctly in JK flipflops