Design Simulation Systems Ltd


Hierarchical Design Example

First, an explanation of how drawings relate to one another may be useful.

When you create a body drawing, you name the pins by selecting 'NAME NET', from the side menu.
If the body belongs to a circuit, you MUST use the same names for any I/O nets which correspond to the pins of the body.
Further, if the device is to be used as a component in another drawing, you MUST name any nets which correspond to the pins of the body as 'NAME\I' (that's backslash uppercase " i ") to tell the netlist compiler that this is an Interface net.

When you save your file, a connectivity file is created of the circuit, ('spice_cn.1.1'), which contains a list of all its components, together with their pin names, as defined on the body.

At the top of the file, is a cross-reference relating the pin names to their local node numbers which, for a top-level circuit, looks like

"VCC"1;
"Y1"3;
"A0"6;
"A1"7;
"B0"16;
"B1"13;
"CIN"10;
"COUT"11;
"Y0"2;

However, if the circuit is actually a component, the pin names will look like this:

"VCC\I"1;
"Y1\I"3;
"A0\I"6;
"A1\I"7;
"B0\I"16;
"B1\I"13;
"CIN\I"10;
"COUT\I"11;
"Y0\I"2;

As previously mentioned, any circuit node that you wish to propagate through a hierarchy, MUST have the suffix "\I" (that's backslash uppercase "i ") to indicate to GSP, the netlist compiler, that it is an Interface node, which will appear in another drawing containing this component.
Failure to do so will result in the compiler being unable to join the component to the circuit. NOTE: Do not name the pins of the body with " \I" suffixes.

The Circuit

This exercise is based on the Berkeley " CPU Killer " example - the 4-Bit Adder netlist, which accompanies the SPICE manual. We will need to construct four drawings from the netlist which, together, comprise a four-level hierarchy, as follows:

4-bit adder
2-bit adder
1-bit adder
NAND gate

The Berkeley example shows .SUBCKT netlists for each of the above, together with a top level circuit, for driving the adder. These, we will reverse-engineer into circuit drawings.

Our hierarchical designs are all performed by

Creating a circuit diagram for the hierarchy level
Creating a body drawing for this level
Adding that body as a component to the next level of hierarchy

Accordingly, we begin at the bottom level of hierarchy, and construct the NAND gate, which is the familiar 7400 circuit, and should appear as shown in the circuit diagram below. The orange node numbers are comments, and are only there to relate the circuit to the Berkeley netlist.

Notice how all interface nets are called " Name\I " to indicate to the netlist compiler, GSP, that this net connects to the outside world.

When we save this drawing, a subdirectory " nand " will be created in the current working directory, under which will be two files discussed earlier: spice.1.1 and spice_cn.1.1.
Next, we construct a body drawing for the gate. Notice that the pin names correspond to the names we gave our interface pins on the circuit, but without the " \I " suffix.

Note: For wires to connect to pins, the pins must be on 0.1 inch grid points. The default grid for a body drawing is " 0.02 1 " , meaning that we have a grid line at every interval of 0.02 inch. This is to aid in the creation of a high resolution drawing. However, when it is time to add the pins, it is best to change to a grid of " 0.02 5 ", which will only show every 5th grid line, and ensure that pins are added at intervals of 0.1 inch.

Pins are added with the ADD PIN command from Menu2, and given names with the NAME NET command on Menu1.

Further, note that the body is approximately centred over the large " X " at the origin of axes. This is the point which determines its attachment to the cursor, when moving the body.

When we save this drawing, the " nand " subdirectory will contain an additional file, named body.1.1.

Now, we can create the one-bit adder, imaginatively called onebit, by adding our NAND gate from Menu1 -> ANALOG -> NAMED PART

As before, note that all interface nets have a " \I " suffix.

We now make a body drawing for it, ensuring that the pin names are the same as our interface nets in the circuit.

We can now create a two bit adder, " twobit " by wiring two of our one bit adders together.

Again, we make a corresponding body drawing.

The two two-bit adders are wired together in the fourbit circuit, finally giving us our four bit adder.

Since we want to use it in a test circuit, we must also create a fourbit body drawing.

Now we have all the pieces in place, so we can create our test circuit, as per the Berkeley netlist

Note, that we can traverse our hierarchy using the PUSH and POP buttons in the menubar, and clicking on the appropriate component. For obvious reasons, this only works on hierarchical drawings, so clicking on SPICE primitives will do nothing.

Running GSP, the netlist compiler, on the top level drawing, produces the following file, "addtest.ckt", to which we manually added the .tran and .print lines, and rename the file "addtest.netlist":

addtest
.tran 1ns 6400ns
.print tran v(1) v(15) v(13) v(14) v(12) v(11) v(16) v(3) v(7) v(6) v(5) v(4) v(9)
*#iplot all
*#run
*#quit
.MODEL QMOD NPN BF=75 RB=100 CJE=1PF CJC=3PF
.MODEL DMOD D
V1 1 0 PULSE 0 3 0 10N 10N 10N 50N
V8 15 0 PULSE 0 3 0 10N 10N 20N 100N
V5 13 0 PULSE 0 3 0 10N 10N 40N 200N
V6 14 0 PULSE 0 3 0 10N 10N 80N 400N
V4 12 0 PULSE 0 3 0 10N 10N 160N 800N
V3 11 0 PULSE 0 3 0 10N 10N 320N 1600N
V9 16 0 PULSE 0 3 0 10N 10N 640N 3200N
V2 3 0 PULSE 0 3 0 10N 10N 1280N 6400N
R1 7 0 1K
R2 9 0 1K
R3 6 0 1K
R4 5 0 1K
R5 4 0 1K
V7 8 0 DC 5
X1 8 7 6 5 4 1 13 11 3 0 9 14 12 16 15 FOURBIT

** VCC:1 Y0:2 Y1:3 Y2:4 Y3:5 A0:6 A1:7 B2:8 B3:9 CIN:10 COUT:12 B1:13 A2:14 A3:15 B0:16
.subckt fourbit 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16
X2 1 2 3 10 6 11 16 13 7 TWOBIT
X14 1 4 5 11 14 12 8 9 15 TWOBIT
.ends fourbit

** VCC:1 Y0:3 Y1:4 CIN:5 A0:6 COUT:7 B0:8 B1:9 A1:10
.subckt twobit 1 3 4 5 6 7 8 9 10
X3 6 8 5 2 3 1 ONEBIT
X13 10 9 2 7 4 1 ONEBIT
.ends twobit

** A:1 B:2 CIN:7 COUT:11 Y:12 VCC:13
.subckt onebit 1 2 7 11 12 13
X4 8 3 13 11 NAND
X5 1 2 13 3 NAND
X6 1 3 13 4 NAND
X7 2 3 13 5 NAND
X8 4 5 13 6 NAND
X9 7 6 13 8 NAND
X10 7 8 13 9 NAND
X11 6 8 13 10 NAND
X12 10 9 13 12 NAND
.ends onebit

** INPUT1:3 INPUT2:4 VCC:6 OUTPUT:11
.subckt nand 3 4 6 11
Q1 11 7 0 QMOD
Q2 8 9 10 QMOD
Q3 2 1 4 QMOD
Q4 2 1 3 QMOD
Q5 9 2 7 QMOD
D1 10 11 DMOD
R6 6 1 4K
R7 7 0 1K
R8 6 8 130
R9 6 9 1.6K
D2 0 3 DMOD
D3 0 4 DMOD
.ends nand
.end

Running the simulation on Spice3 gave these results:

Readers are encouraged to check the correctness of the adder 's arithmetic...

Back to Home Page