Overview
The simulation primitive elements provided in the library "laplace" permit the behavioural modelling of analogue systems and circuits with the ultimate in behavioural description languages, the Laplace transfer function. If you didn't learn Laplace Transforms at college, go and find out  it'll let you describe and simulate a system without actually knowing how to design the hardware. That goes for mechanical, as well as electrical systems. A transfer function is defined as:
H(s) = Y(s) / U(s) where Y(s) is the Laplace transform of the output, and U(s) is the Laplace transform of the input. The form of both numerator and denominator is a polynomial expression, where the numerator can be represented by:
B0.s^m + B1.s^m1 + B2.s^m2.....+ Bm1.s + Bm while the denominator looks like:
s^n + A1.s^n1 + A2.s^n2........+ An1.s + An For a realizeable system, the order of the numerator will be less than or equal to, the order of the denominator. For any given transfer function, both numerator and denominator are first multiplied by s^n times an arbitrary function, E(s), (eqivalent to dividing by the highest power of s times an arbitrary function). Y(s) then becomes:
E(s).B0.s^mn + E(s).B1.s^mn1 + E(s).B2.s^mn2 .....+ E(s).Bm1.s^1n + E(s).Bm.sn and U(s) becomes:
E(s) + E(s).A1.s^1 + E(s).A2.s^2........ + E(s).An1.s^1n + E(s).An.s^n which may be written:
E(s) = U(s)  E(s).A1.s^1  E(s).A2.s^2....  E(s).An1.s^1n  E(s).An.s^n Using only integrator (for 1/s), adder and constantmultiplier elements, it is possible to realize this type of function within SPICE, using summation as the arbitrary function, E(s).
> [ADD]> Vout  ^   [MULTIPLY BY B0] [MULTIPLY BY B1] ^ ^ E(s)  (1/s)  Vin>[ADD]>>[INTEGRATE]> ^    <[MULTIPLY BY A1]<
The above diagram is one n"th of the number needed for a given denominator polynomial, and may be cascaded from Vout to Vin, with the input adder taking in an extra term from the succeeding stage, and the output adder being placed after the last stage.. E(s) appears as an apparent feedback error signal, while the ADD at the top right implements Y(s). The integrator (1/s) function serves to provide the "n" integrations, to form all of the E(s) terms in the above equations, where "n" is the order of the denominator polynomial. The terms B0, B1, A1, etc are the coefficients of the polynomial, applied through constantgain multipliers. Provision is made for the same order in the numerator as the denominator, so the unused coefficients may merely be set to zero. The above block has been made generic, by applying the coefficients as dc voltages, and grounding any unused coefficient inputs. Thus, one block may be cascaded "n" times, and "m" coefficients may be defined, to simulate any transfer function. The block is supplied in two forms, for use with Spice3 and SPICE2G6, and the blocks are entitled "3TFE" ("Transfer Function Element") and "TFE" respectively. Multiinput adders are provided, with the same naming convention, i.e, a 5 input adder for use with Spice3, is called "3ADD5" etc. Additionally, to cater for gain from the highorder stage, an adder with one weighted input is supplied, named "3WADD2" or "WADD2", which may be cascaded with any other adder to form a weighted sum. The following examples have been included to make the principle clear, and to provide a template for future designs:
Chebyshev Filter example
The transfer function of the filter is:
(0.7157) / (s^3 + 1.2529s^2 + 1.5349s + 0.7157) Dividing top and bottom by s^3 gives:
(0.7157s^3) / (1 + 1.2529s^1 + 1.5349s2 + 0.7157s^3) Since the numerator is a pure number, we will need a weighted adder at the output but, since there are no other numerator terms, all forward coefficients may be either grounded, or set to DC 0 volts. Since there are three terms in the denominator, three cascaded transfer function elements will be required, to supply s^1, s^2 and s^3, and the three voltage sources defining the coefficients will have values of (1.2529v), (1.5349v) and (0.7157v). The weighting function of the output from the last stage will be (0.7157) and we will need one fourinput adder at the input. For reasons of simplicity, the topology has been left constant, and there is a second adder at the output, but all its inputs are zero.
