.LP
Examples:
.LP
CBYP 13 0 1UF
COSC 17 23 10U IC=3V
LLINK 42 69 1UH
LSHUNT 23 51 10U IC=15.7MA
.LP
N+ and N are the positive and negative element nodes, respectively.
VALUE is the capacitance in Farads or the inductance in Henries.
For the capacitor, the (optional) initial condition is the initial
(timezero) value of capacitor voltage (in Volts). For the inductor,
the (optional) initial condition is the initial (timezero) value
of inductor current (in Amps) that flows from N+, through the inductor,
to N. Note that the initial conditions (if any) apply 'only' if
the UIC option is specified on the .TRAN card.
.LP
.NH 2
Coupled (Mutual) Inductors
.LP
General form:
.LP
.NH 2
KXXXXXXX LYYYYYYY LZZZZZZZ VALUE
.LP
Examples:
.LP
K43 LAA LBB 0.999
KXFRMR L1 L2 0.87
.LP
LYYYYYYY and LZZZZZZZ are the names of the two coupled inductors,
and VALUE is the coefficient of coupling, K, which must be greater
than 0 and less than or equal to 1. Using the 'dot' convention,
place a 'dot' on the first node of each inductor.
.LP
.NH 2
Transmission Lines (Lossless)
.LP
General form:
.LP
.NH 2
TXXXXXXX N1 N2 N3 N4 Z0=VALUE
+>
+
.LP
Examples:
.LP
T1 1 0 2 0 Z0=50 TD=10NS
.LP
N1 and N2 are the nodes at port 1; N3 and N4 are the nodes at port 2.
Z0 is the characteristic impedance.
.LP
The length of the line may be expressed in either of two forms.
.LP
The transmission delay, TD, may be specified directly (as TD=10ns,
for example). Alternatively, a frequency F may be given, together
with NL, the normalized electrical length of the transmission line
with respect to the wavelength in the line at the frequency F.
.LP
If a frequency is specified but NL is omitted, 0.25 is assumed
(that is, the frequency is assumed to be the quarterwave frequency).
Note that although both forms for expressing the line length are
indicated as optional, one of the two must be specified.
.LP
Note that this element models only one propagating mode. If all
four nodes are distinct in the actual circuit, then two modes may
be excited. To simulate such a situation, two transmission line
elements are required. (see the example in Appendix A for further
clarification.)
.LP
The (optional) initial condition specification consists of the
voltage and current at each of the transmission line ports. Note
that the initial conditions (if any) apply 'only' if the UIC option is specified on the .TRAN card.
.LP
One should be aware that SPICE will use a transient timestep
which does not exceed 1/2 the minimum transmission line delay.
Therefore very short transmission lines (compared with the analysis
time frame) will cause long run times.
.LP
.NH 2
Linear Dependent Sources
.LP
SPICE allows circuits to contain linear dependent sources characterized
by any of the four equations
.LP
i=g*v v=e*v i=f*i v=h*i
.LP
where g, e, f, and h are constants representing transconductance,
voltage gain, current gain, and transresistance, respectively.
.LP
Note: a more complete description of dependent sources as implemented
in SPICE is given in Appendix B.
.LP
.NH 2
Linear VoltageControlled Current Sources
.LP
General form:
.LP
.SH
GXXXXXXX N+ N NC+ NC VALUE
.LP
Examples:
.LP
G1 2 0 5 0 0.1MMHO
.LP
N+ and N are the positive and negative nodes, respectively. Current
flow is from the positive node, through the source, to the negative
node. NC+ and NC are the positive and negative controlling nodes,
respectively. VALUE is the transconductance (in mhos).
.LP
.NH 2
Linear VoltageControlled Voltage Sources
.LP
General form:
.LP
.SH
EXXXXXXX N+ N NC+ NC VALUE
.LP
Examples:
.LP
E1 2 3 14 1 2.0
.LP
N+ is the positive node, and N is the negative node. NC+ and NC
are the positive and negative controlling nodes, respec18 tively.
VALUE is the voltage gain.
.LP
.NH 2
Linear CurrentControlled Current Sources
.LP
General form:
.LP
.SH
FXXXXXXX N+ N VNAM VALUE
.LP
Examples:
.LP
F1 13 5 VSENS 5
.LP
N+ and N are the positive and negative nodes, respectively. Current
flow is from the positive node, through the source, to the negative
node. VNAM is the name of a voltage source through which the controlling
current flows. The direction of positive controlling current flow
is from the positive node, through the source, to the negative
node of VNAM. VALUE is the current gain.
.LP
.NH 2
Linear CurrentControlled Voltage Sources
.LP
General form:
.LP
.SH
HXXXXXXX N+ N VNAM VALUE
.LP
Examples:
.LP
HX 5 17 VZ 0.5K
.LP
N+ and N are the positive and negative nodes, respectively. VNAM
is the name of a voltage source through which the controlling current
flows. The direction of positive controlling current flow is from
the positive node, through the source, to the negative node of
VNAM. VALUE is the transresistance (in ohms).
.LP
.NH 2
NonLinear Dependent Sources
.LP
General form:
.LP
.SH
BXXXXXXX N+ N
.LP
Examples:
.LP
B1 0 1 I=COS(V(1))+SIN(V(2))
B1 0 1 V=LN(COS(LOG(V(1)V(2)^2)))V(3)^4+V(2)^V(1)
B1 3 4 I=17
B1 3 4 V=EXP(PI^I(VDD))
.LP
.LP
.LP
N+ is the positive node and N is the negative node.
.LP
The values of the 'V' and 'I' parameters determine the voltages and
currents across and through the device, respectively.
.LP
If 'I' is given, then the device is a current source, and if 'V' is
given then the device is a voltage source.
.LP
One, and only one, of these parameters must be given.
.LP
The expressions, EXPR, given for 'V' and 'I' may be any function of
voltages and currents through voltage sources in the system. The
following functions of real variables are defined:
.LP
abs asinh cosh sin
acos atan exp sinh
acosh atanh ln sqrt
asin cos log tan
.LP
The following operations are defined:
.LP
+  * / unary 
.LP
If the values of the circuit variables used in the expressions enter
a region where the value of the expression or any of its partial
derivatives becomes undefined, an error results.
.LP
.NH 2
Independent Sources
.LP
General form:
.LP
.SH
VXXXXXXX N+ N < DC/TRAN VALUE> >>
+ >> >>
.LP
IYYYYYYY N+ N < DC/TRAN VALUE> >>
+ >> >>
.LP
Examples:
.LP
VCC 10 0 DC 6
VIN 13 2 0.001 AC 1 SIN(0 1 1MEG)
ISRC 23 21 AC 0.333 45.0 SFFM(0 1 10K 5 1K)
VMEAS 12 9
VCARRIER 1 0 DISTOF1 0.1 90.0
VMOD 2 0 DISTOF2 0.01
IIN 1 5 AC 1 DISTOF1 DISTOF2 0.001
.LP
N+ and N are the positive and negative nodes, respectively. Note
that voltage sources need not be grounded. Positive current is
assumed to flow from the positive node, through the source, to
the negative node. A current source of positive value, will force
current to flow out of the N+ node, through the source, and into the N node.
.LP
Voltage sources, in addition to being used for circuit excitation,
are the 'ammeters' for SPICE, that is, zero valued voltage sources
may be inserted into the circuit for the purpose of measuring current.
They will, of course, have no effect on circuit operation since they
represent shortcircuits.
.LP
DC/TRAN is the dc and transient analysis value of the source. If
the source value is zero both for dc and transient analyses, this
value may be omitted.
.LP
If the source value is timeinvariant (e.g., a power supply), then
the value may optionally be preceded by the letters DC.
.LP
ACMAG is the ac magnitude and ACPHASE is the ac phase. The source
is set to this value in the ac analysis. If ACMAG is omitted following
the keyword AC, a value of unity is assumed. If ACPHASE is omitted,
a value of zero is assumed.
.LP
If the source is not an ac smallsignal input, the keyword AC and
the ac values are omitted.
.LP
DISTOF1 and DISTOF2 are the keywords that specify that the independent
source has distortion inputs at the frequencies F1 and F2 respectively.
See the description of the DISTO control line.
.LP
The keywords may be followed by an optional magnitude and phase. The
default values of the magnitude and phase are 1.0 and 0.0 respectively.
.LP
Any independent source can be assigned a timedependent value for
transient analysis. If a source is assigned a timedependent value,
the timezero value is used for dc analysis.
.LP
There are five independent source functions:
.LP
pulse, exponential, sinusoidal, piecewise linear, and singlefrequency FM.
.LP
If parameters other than source values are omitted or set to zero,
the default values shown will be assumed.
.LP
(TSTEP is the printing increment and TSTOP is the final time (see
the .TRAN line for explanation)).
.LP
.NH 3
Pulse PULSE(V1 V2 TD TR TF PW PER)
.LP
Examples:
.LP
VIN 3 0 PULSE(1 1 2NS 2NS 2NS 50NS 100NS)
.LP
.SH
parameters default values units
.LP
V1 (initial value) Volts or Amps
V2 (pulsed value) Volts or Amps
TD (delay time) 0.0 seconds
TR (rise time) TSTEP seconds
TF (fall time) TSTEP seconds
PW (pulse width) TSTOP seconds
PER (period) TSTOP seconds
.LP
A single pulse so specified is described by the following table:
.LP
.SH
time value
.LP
0 V1
TD V1
TD+TR V2
TD+TR+PW V2
TD+TR+PW+TF V1
TSTOP V1
.LP
Intermediate points are determined by linear interpolation.
.LP
.NH 3
Sinusoidal SIN(VO VA FREQ TD THETA)
.LP
Examples:
.LP
VIN 3 0 SIN(0 1 100MEG 1NS 1E10)
.LP
.SH
parameters default value units
.LP
VO (offset) Volts or Amps
VA (amplitude) Volts or Amps
FREQ (frequency) 1/TSTOP Hz
TD (delay) 0.0 seconds
THETA (damping factor) 0.0 1/seconds
.LP
The shape of the waveform is described by the following table:
.LP
.SH
time value
.LP
0 to TD VO
TD to TSTOP VO+VA*exp((timeTD)*THETA)
*sine(twopi*FREQ*(time+TD))
.LP
.NH 3
Exponential EXP(V1 V2 TD1 TAU1 TD2 TAU2)
.LP
Examples:
.LP
VIN 3 0 EXP(4 1 2NS 30NS 60NS 40NS)
.LP
.SH
parameters default values units
.LP
V1 (initial value) Volts or Amps
V2 (pulsed value) Volts or Amps
TD1 (rise delay time) 0.0 seconds
TAU1 (rise time constant) TSTEP seconds
TD2 (fall delay time) TD1+TSTEP seconds
TAU2 (fall time constant) TSTEP seconds
.LP
The shape of the waveform is described by the following table:
.LP
.SH
time value
.LP
0 to TD1 V1
TD1 to TD2 V1+(V2V1)*(1exp((timeTD1)/TAU1))
TD2 to TSTOP V1+(V2V1)*(1exp((timeTD1)/TAU1))
+(V1V2)*(1exp((timeTD2)/TAU2))
.LP
.NH 3
PieceWise Linear PWL(T1 V1 )
.LP
Examples:
.LP
VCLOCK 7 5 PWL(0 7 10NS 7 11NS 3 17NS 3 18NS 7 50NS 7)
.LP
Parameters and default values
.LP
Each pair of values (Ti, Vi) specifies that the value of the source is Vi (in
Volts or Amps) at time=Ti. The value of the source at intermediate
values of time is determined by using linear interpolation on the input values.
.LP
.NH 3
SingleFrequency FM
.LP
.SH
SFFM(VO VA FC MDI FS)
.LP
Examples:
.LP
V1 12 0 SFFM(0 1M 20K 5 1K)
.LP
.SH
parameters default values units
.LP
VO (offset) Volts or Amps
VA (amplitude) Volts or Amps
FC (carrier frequency) 1/TSTOP Hz
MDI (modulation index)
FS (signal frequency) 1/TSTOP Hz
.LP
The shape of the waveform is described by the following equation:
.LP
value = VO + VA*sine((twopi*FC*time) + MDI*sine(twopi*FS*time))
.LP
.NH 2
Switches
.LP
General form:
.LP
.SH
SXXXXXXX N+ N NC+ NC MNAME
WXXXXXXX N+ N VNAME MNAME
.LP
Examples:
.LP
S1 1 2 3 4 SWITCH1 ON
S2 5 6 3 0 SM2 OFF
SWITCH1 1 2 10 0 SMODEL1
W1 1 2 VCLOCK SWITCHMOD1
W2 3 0 VRAMP SM1 ON
WRESET 5 6 VCLCK LOSSYSWITCH OFF
.LP
Nodes N+ and N are the nodes between which the switch terminal are
connected. For the voltagecontrolled switch, nodes NC+ and NC are
the positive and negative controlling nodes respectively. For the
currentcontrolled switch, the controlling current is that through
the VNAME, the specified voltage source.
.LP
The direction of positive controlling current flow is from the positive node,
through the source, to the negative node.
.bp
.NH
SEMICONDUCTOR DEVICES
.LP
The elements that have been described to this point typically require
only a few parameter values to specify completely the electrical
characteristics of the element.
.LP
However, the models for the four semiconductor devices that are
included in the SPICE program require many parameter values. Moreover,
many devices in a circuit often are defined by the same set of
device model parameters.
.LP
For these reasons, a set of device model parameters is defined
on a separate .MODEL line and assigned a unique model name. The
device element lines in SPICE then reference the model name. This
scheme alleviates the need to specify all of the model parameters
on each device element card.
.LP
Each device element line contains the device name, the nodes to
which the device is connected, and the device model name. In addition,
other optional parameters may be specified for each device: geometric
factors and an initial condition.
.LP
The area factor used on the diode, BJT and JFET device line determines
the number of equivalent parallel devices of a specified model. The
affected parameters are marked with an asterisk under the heading 'area'
in the model descriptions below. Several geometric factors
associated with the channel and the drain and source diffusions
can be specified on the MOSFET device card.
.LP
Two different forms of initial conditions may be specified for devices.
.LP
The first form is included to improve the dc convergence for circuits
that contain more than one stable state. If a device is specified
OFF, the dc operating point is determined with the terminal voltages
for that device set to zero. After convergence is obtained, the
program continues to iterate to obtain the exact value for the
terminal voltages.
.LP
If a circuit has more than one dc stable state, the OFF option
can be used to force the solution to correspond to a desired state.
If a device is specified OFF when in reality the device is conducting,
the program will still obtain the correct solution (assuming the
solutions converge) but more iterations will be required since
the program must independently converge to two separate solutions.
.LP
The .NODESET line serves a similar purpose as the OFF option. The .NODESET
option is easier to apply and is the preferred means to aid convergence.
.LP
The second form of initial conditions are specified for use with
the transient analysis. These are true 'initial conditions' as
opposed to the convergence aids above. See the description of the .IC card
and the .TRAN line for a detailed explanation of initial conditions.
.LP
.NH 2
Semiconductor Resistors
.LP
General form:
.LP
.SH
RXXXXXXX N+ N MNAME
.LP
Examples:
.LP
RLOAD 2 10 10K
RMOD 3 7 RMODEL L=10u W=1u
.LP
This is the more general form, of the resistor presented in section 6.1,
and allows the modelling of temperature effects and for the calculation of
the actual resistance value from strictly geometric information, and the
specification of the process.
.LP
If VALUE is specified, it overrides the geometric information and defines the
resistance.
.LP
If MNAME is specified, then the resistance may be calculated from the
process information in the model MNAME and the given LENGTH and WIDTH.
.LP
If VALUE is not specified, then MNAME and LENGTH must be specified.
.LP
If WIDTH is not specified, then it is taken from the default width given in
the model.
.LP
The (optional) TEMP value is the temperature at which this device
is to operate, and overrides the temperature specification on the .OPTIONS
control line.
.LP
.NH 2
Semiconductor Capacitors
.LP
General form:
.LP
.SH
CXXXXXXX N+ N MNAME
.LP
Examples:
.LP
CLOAD 2 10 10P
CMOD 3 7 CMODEL L=10u W=1u
.LP
This is the more general form of the capacitor presented in section 6.2,
and allows for the calculation of the actual capacitance value from
strictly geometric information, and the specification of the process.
.LP
If VALUE is specified, it overrides the geometric information and defines the
capacitance.
.LP
If MNAME is specified, then the capacitance may be calculated from the
process information in the model MNAME and the given LENGTH and WIDTH.
.LP
If VALUE is not specified, then MNAME and LENGTH must be specified.
.LP
If WIDTH is not specified, then it is taken from the default width given in
the model.
.LP
Either VALUE or MNAME, LENGTH and WIDTH may be specified, but not both sets.
.LP
.NH 2
Uniform Distributed RC Lines
.LP
General form:
.LP
.SH
UXXXXXXX N1 N2 N3 MNAME
.LP
Examples:
.LP
U1 1 2 0 URCMOD L=50U
URC2 1 12 2 UMODL L=1mil N=6
.LP
N1 and N2 are the two element nodes the RC line connects, while N3 is
the node to which the capacitances are connected.
.LP
MNAME is the model name, LENGTH is the length of the RC line in metres.
.LP
LUMPS, if specified, is the number of lumped segments to use in modelling
the RC line. See the model description for the action taken if this
parameter is omitted.
.LP
.NH 2
Junction Diodes
.LP
General form:
.LP
.SH
DXXXXXXX N+ N MNAME
.LP
Examples:
.LP
DBRIDGE 2 10 DIODE1
DCLMP 3 7 DMOD 3.0 IC=0.2
.LP
N+ and N are the positive and negative nodes, respectively. MNAME
is the model name, AREA is the area factor, and OFF indicates an
(optional) starting condition on the device for dc analysis. If
the area factor is omitted, a value of 1.0 is assumed. The (optional)
initial condition specification using IC=VD is intended for use
with the UIC option on the .TRAN card, when a transient analysis is
desired starting from other than the quiescent operating point.
.LP
.NH 2
Bipolar Junction Transistors (BJT's)
.LP
General form:
.LP
.SH
QXXXXXXX NC NB NE MNAME
+
.LP
Examples:
.LP
Q23 10 24 13 QMOD IC=0.6,5.0
Q50A 11 26 4 20 MOD1
.LP
NC, NB, and NE are the collector, base, and emitter nodes, respectively.
NS is the (optional) substrate node. If unspecified, ground is used.
MNAME is the model name, AREA is the area factor, and OFF indicates
an (optional) initial condition on the device for the dc analysis.
If the area factor is omitted, a value of 1.0 is assumed.
.LP
The (optional) initial condition specification using IC=VBE,VCE
is intended for use with the UIC option on the .TRAN card, when a
transient analysis is desired starting from other than the quiescent
operating point. See the .IC line description for a better way to set
transient initial conditions.
.LP
.NH 2
Junction FieldEffect Transistors (JFET's)
.LP
General form:
.LP
.SH
JXXXXXXX ND NG NS MNAME
.LP
Examples:
.LP
J1 7 2 3 JM1 OFF
.LP
ND, NG, and NS are the drain, gate, and source nodes, respectively.
MNAME is the model name, AREA is the area factor, and OFF indicates
an (optional) initial condition on the device for dc analysis.
If the area factor is omitted, a value of 1.0 is assumed.
.LP
The (optional) initial condition specification, using IC=VDS,VGS
is intended for use with the UIC option on the .TRAN card, when a
transient analysis is desired starting from other
than the quiescent operating point (see the .IC line for a better way
to set initial conditions).
.LP
.NH 2
MOSFET's
.LP
General form:
.LP
.SH
MXXXXXXX ND NG NS NB MNAME
+ +
+
.LP
Examples:
.LP
M1 24 2 0 20 TYPE1
M31 2 17 6 10 MODM L=5U W=2U
M31 2 16 6 10 MODM 5U 2U
M1 2 9 3 0 MOD1 L=10U W=5U AD=100P AS=100P PD=40U PS=40U
M1 2 9 3 0 MOD1 10U 5U 2P 2P
.LP
ND, NG, NS, and NB are the drain, gate, source, and bulk (substrate)
nodes, respectively.
.LP
MNAME is the model name.
.LP
L and W are the channel length and width, in meters.
.LP
AD and AS are the areas of the drain and source diffusions, in sqmeters.
.LP
Note that the suffix U specifies microns (1E6 m) and P sqmicrons
(1E12 sqm).
.LP
If any of L, W, AD, or AS are not specified, default values are used.
.LP
The user may specify the values to be used for these default parameters
on the .OPTIONS card. The use of defaults simplifies input file
preparation, as well as the editing required if device geometries
are to be changed.
.LP
PD and PS are the perimeters of the drain and source junctions, in meters.
.LP
NRD and NRS designate the equivalent number of squares of the drain
and source diffusions; these values multiply the sheet resistance
RSH specified on the .MODEL line for an accurate representation
of the parasitic series drain and source resistance of each transistor.
.LP
PD and PS default to 0.0 while NRD and NRS to 1.0.
.LP
OFF indicates an (optional) initial condition on the device for
dc analysis. The (optional) initial condition specification using
IC=VDS,VGS,VBS is intended for use with the UIC option on the .TRAN
card, when a transient analysis is desired starting from other
than the quiescent operating point. See the .IC line for a better and
more convenient way to specify transient initial conditions.
.NH 2
.MODEL Line
.LP
General form:
.LP
.SH
.MODEL MNAME TYPE(PNAME1=PVAL1 PNAME2=PVAL2 ... )
.LP
Examples:
.LP
.MODEL MOD1 NPN BF=50 IS=1E13 VBF=50
.LP
The .MODEL line specifies a set of model parameters that will be
used by one or more devices. MNAME is the model name, and type
is one of the following fourteen types:
.LP
R silicon resistor
C silicon capacitor
URC Uniform Distributed RC line
D diode model
NPN NPN BJT model
PNP PNP BJT model
NJF Nchannel JFET model
PJF Pchannel JFET model
NMOS Nchannel MOSFET model
PMOS Pchannel MOSFET model
NMF Nchannel MOSFET model
PMF Pchannel MOSFET model
SW voltagecontrolled switch
CSW currentcontrolled switch
.LP
Parameter values are defined by appending the parameter name, as
given below for each model type, followed by an equal sign and
the parameter value. Model parameters that are not given a value
are assigned the default values given below for each model type.
.LP
.NH 2
Resistor Model
.LP
The resistor model consists of processrelated device data that allow the
resistance to be calculated from geometric information and to be corrected
for temperature. The parameters available are:
.LP
.SH
name parameter units default example
.LP
TC1 1st order temp coeff ohm/degC 0.0
TC2 2nd order temp coeff ohm/degC 0.0
RSH sheet resistance ohm/sq  50
DEFW default width metres 1e6 2e6
NARROW narrowing due to
side etching metres 0.0 1e7
TNOM parameter measurement temp degC 27 50
.LP
The sheet resistance is used with the narrowing parameter and L and W
from the resistor device to determine the nominal resistance by the
formula:
.LP
R = RSH * (LNARROW) / (WNARROW)
.LP
DEFW is used to supply a default value for W if one is not specified for
the device. If either RSH or L is not specified, then the standard default
resistance value of 1K is used. TNOM is used to override the circuitwide value
given on the .OPTIONS control line where the parameters of this model have
been measured at a different temperature. After the nominal resistance is
calculated, it is adjusted for temperature by the formula:
.LP
R(t) = R(t0)[1+TC1(tt0) + TC2(tt0)**2]
.LP
.NH 2
Capacitor Model
.LP
The capacitor model contains process information that may be used to compute
the capacitance from strictly geometric information.
.LP
.SH
name parameter units default example
.LP
CJ junction bottom cap F/m**2  5e5
CJSW junction sidewall cap F/m**2  2e11
DEFW default width metres 1e6 2e6
NARROW narrowing due to
side etching metres 0.0 1e7
.LP
The capacitor has a capacitance computed as:
.LP
CAP = CJ(LENGTHNARROW)(WIDTHNARROW) +
2.CJSW(LENGTH + WIDTH  2.NARROW)
.LP
.NH 2
Uniform Distributed RC Model
.LP
The URC model is derived from a model proposed by L.Gertzberg in 1974.
The model is accomplished by a subcircuittype expansion of the URC line
into a network of lumped RC segments with internallygenerated nodes.
The RC segments are in a geometric progression, increasing toward the
middle of the URC line, with K as a proportionality constant. The number
of lumped segments used, if not specified for the URC line device, is
determined by the following formula:
.LP
N = log[Fmax(R/L)(C/L)(TWOPI.L**2)((KI)/K)**2] / logK
.LP
The URC line is made up strictly of resistor and capacitor segments unless
the ISPERL parameter is given a nonzero value, in which case the capacitors
are replaced with reversebiased diodes with a zerobias junction capacitance
equivalent to the capacitance replaced, and with a saturation current of
ISPERL amps per metre of transmission line and an optional series resistance
equivalent to RSPERL ohms per metre.
.LP
.SH
name parameter units default example
.LP
K Propagation constant 2.0 1.25
FMAX Max freq of interest Hz 1.0G 6.5Meg
RPERL Res per unit length ohm/m 1000 10
CPERL cap per unit length F/m 1.0e15 1pF
ISPERL sat current per
unit length A/m 0 
RSPERL Diode res per unit
length ohm/m 0 
.LP
.NH 2
Switch Model
.LP
The switch model allows an almost ideal switch to be described in SPICE.
The switch is not quite ideal in that the resistance cannot change from 0
to infinity, but must always have a finite positive value. By proper selection
of the on and off resistances, they can be effectively zero and infinity in
comparison to other circuit elements. The parameters available are:
.LP
.SH
name parameter units default switch
.LP
VT threshold voltage volts 0.0 S
IT threshold current amps 0.0 W
VH hysteresis voltage volts 0.0 S
VH hysteresis current amps 0.0 W
RON on resistance ohms 1.0 both
ROFF off resistance ohms 1/GMIN both
.LP
See the .OPTIONS control line for a description of GMIN, whose default
value results in an off resistance of 1E+12 ohms.
.LP
The use of an ideal element that is highly nonlinear such as a switch
can cause large discontinuities to occur in the circuit node voltages.
A rapid change such as that associated with a switch changing state can
cause numerical roundoff or tolerance problems leading to erroneous
results or timestep difficulties. The user of switches can improve the
situation by taking the following steps:
.LP
First of all it is wise to set ideal switch impedances only high and low
enough to be negligible with respect to other circuit elements. Using
switch impedances that are close to "ideal" in all cases aggravates the
problem of discontinuities mentioned above. Of course, when modelling real
devices such as MOSFETS, the onresistance should be adjusted to a realistic
level depending on the size of the device being modelled.
.LP
If a wide range of ON to OFF resistances must be used in the switches,
(ROFF/RON > 1E12) then the tolerance on errors allowed during transient
analysis should be increased using the .OPTIONS control line and specifying
TRTOL to be less than the default value of 7.0. When switches are placed
around capacitors, then the option CHGTOL should also be reduced. Suggested
values for these two options are 1.0 and 1E16 respectively. These changes
inform SPICE3 to be more careful around the switch points so that no errors
are made due to the rapid change in the circuit.
.LP
.NH 2
Diode Model
.LP
The dc characteristics of the diode are determined by the parameters
IS and N. An ohmic resistance, RS, is included. Charge storage
effects are modeled by a transit time, TT, and a nonlinear depletion
layer capacitance which is determined by the parameters CJO, VJ,
and M. The temperature dependence of the saturation current is
defined by the parameters EG, the energy and XTI, the saturation
current temperature exponent. Reverse breakdown is modeled by an
exponential increase in the reverse diode current and is determined
by the parameters BV and IBV (both of which are positive numbers).
.LP
.SH
name parameter units default example
.LP
1 IS saturation current A 1.0E14 1.0E14
2 RS ohmic resistance Ohm 0 10
3 N emission coefficient 1 1.0
4 TT transittime sec 0 0.1Ns
5 CJO zerobias junction cap F 0 2PF
6 VJ junction potential V 1 0.6
7 M grading coefficient 0.5 0.5
8 EG activation energy eV 1.11 1.11 Si
0.69 Sbd
0.67 Ge
9 XTI saturationcurrent temp. exp 3.0 3.0 jn
2.0 Sbd
10 KF flicker noise coefficient 0
11 AF flicker noise exponent 1
12 FC coefficient for forwardbias 0.5
depletion capacitance formula
13 BV reverse breakdown voltage V infinite 40.0
14 IBV current at breakdown voltage A 1.0E3
.LP
.NH 2
BJT Models (both NPN and PNP)
.LP
The bipolar junction transistor model in SPICE is an adaptation
of the integral charge control model of Gummel and Poon. This modified
GummelPoon model extends the original model to include several
effects at high bias levels.
.LP
The model will automatically simplify to the simpler EbersMoll
model when certain parameters are not specified.
.LP
The parameter names used in the modified GummelPoon model have
been chosen to be more easily understood by the program user, and
to reflect better both physical and circuit design thinking.
.LP
The dc model is defined by the parameters IS, BF, NF, ISE, IKF,
and NE which determine the forward current gain characteristics,
IS, BR, NR, ISC, IKR, and NC which determine the reverse current
gain characteristics, and VAF and VAR which determine the output
conductance for forward and reverse regions.
.LP
Three ohmic resistances RB, RC, and RE are included, where RB can
be high current dependent.
.LP
Base charge storage is modeled by forward and reverse transit times,
TF and TR, the forward transit time TF being bias dependent if
desired, and nonlinear depletion layer capacitances which are determined
by CJE, VJE, and MJE for the BE junction , CJC, VJC, and MJC for
the BC junction and CJS, VJS, and MJS for the CS (CollectorSubstrate)
junction.
.LP
The temperature dependence of the saturation current, IS, is determined
by the energygap, EG, and the saturation current temperature exponent,
XTI. Additionally base current temperature dependence is modeled
by the beta temperature exponent XTB in the new model.
.LP
The BJT parameters used in the modified GummelPoon model are listed
below. The parameter names used in earlier versions of SPICE2 are
still accepted.
.LP
.SH
Modified GummelPoon BJT Parameters.
.LP
.SH
name parameter units default example
.LP
IS transport saturation current A 1.0E16 1.0E15
BF ideal maximum forward beta 100 100
NF forward current emission
coefficient 1.0 1
VAF forward Early voltage V infinite 200
IKF corner for forward beta
high current rolloff A infinite 0.01
ISE BE leakage saturation
current A 0 1.0E13
NE BE leakage emission
coefficient 1.5 2
BR ideal maximum reverse beta 1 0.1
NR reverse current emission
coefficient 1 1
VAR reverse Early voltage V infinite 200
IKR corner for reverse beta
high current rolloff A infinite 0.01
ISC BC leakage saturation
current A 0 1.0E13
NC BC leakage emission
coefficient 2 1.5
RB zero bias base resistance Ohms 0 100
IRB current where base resistance
falls halfway to its min value A infinite 0.1
RBM minimum base resistance
at high currents Ohms RB 10
RE emitter resistance Ohms 0 1
RC collector resistance Ohms 0 10
CJE BE zerobias depletion
capacitance F 0 2PF
VJE BE builtin potential V 0.75 0.6
MJE BE junction exponential
factor 0.33 0.33
TF ideal forward transit time sec 0 0.1Ns
XTF coefficient for bias
dependence of TF 0
VTF voltage describing VBC
dependence of TF V infinite
ITF highcurrent parameter for
effect on TF A 0
PTF excess phase at
freq=1.0/(TF*2PI) Hz deg 0
CJC BC zerobias depletion
capacitance F 0
2PF *
VJC BC builtin potential V 0.75 0.5
MJC BC junction exponential
factor 0.33 0.5
XCJC fraction of BC depletion
capacitance 1 connected to
internal base node
TR ideal reverse transit time sec 0 10Ns
CJS zerobias collectorsubstrate
capacitance F 0
2PF *
VJS substrate junction builtin
potential V 0.75
MJS substrate junction exponential
factor 0 0.5
XTB forward and reverse beta
temperature exponent 0
EG energy gap for temperature effect
on IS eV 1.11
XTI temperature exponent for effect
on IS 3
KF flickernoise coefficient 0
AF flickernoise exponent 1
FC coefficient for forwardbias
depletion capacitance formula 0.5
.LP
.NH 2
JFET Models (both N and P Channel)
.LP
The JFET model is derived from the FET model of Shichman and Hodges.
The dc characteristics are defined by the parameters VTO and BETA,
which determine the variation of drain current with gate voltage,
LAMBDA, which determines the output conductance, and IS, the saturation
current of the two gate junctions.
.LP
Two ohmic resistances, RD and RS, are included. Charge storage
is modeled by nonlinear depletion layer capacitances for both gate
junctions which vary as the 1/2 power of junction voltage and
are defined by the parameters CGS, CGD, and PB.
.LP
.SH
name parameter units default example
.LP
VTO threshold voltage V 2.0 2.0
BETA transconductance
parameter A/V**2 1.0E4 1.0E3
LAMBDA channel length
modulation parameter 1/V 0 1.0E4
RD drain ohmic resistance Ohm 0 100
RS source ohmic resistance Ohm 0 100
CGS zerobias GS
junction capacitance F 0 5PF
CGD zerobias GD
junction capacitance F 0 1PF
PB gate junction potential V 1 0.6
IS gate junction saturation
current A 1.0E14 1.0E14
KF flicker noise coefficient 0
AF flicker noise exponent 1
FC coefficient for forwardbias 0.5
depletion capacitance formula
.LP
.NH 2
MOSFET Models (both N and P channel)
.LP
SPICE provides three MOSFET device models which differ in the formulation
of the IV characteristic. The variable LEVEL specifies the model to be used:
.LP
LEVEL=1 > ShichmanHodges
LEVEL=2 > MOS2 (as described in [1])
LEVEL=3 > MOS3, a semiempirical model(see [1])
.LP
The dc characteristics of the MOSFET are defined by the device
parameters VTO, KP, LAMBDA, PHI and GAMMA. These parameters are
computed by SPICE if process parameters (NSUB, TOX, ...) are given,
but userspecified values always override.
.LP
VTO is positive (negative) for enhancement mode and negative (positive)
for depletion mode Nchannel (Pchannel) devices.
.LP
Charge storage is modeled by three constant capacitors, CGSO, CGDO,
and CGBO which represent overlap capacitances, by the nonlinear
thinoxide capacitance which is distributed among the gate, source,
drain, and bulk regions, and by the nonlinear depletionlayer capacitances
for both substrate junctions divided into bottom and periphery,
which vary as the MJ and MJSW power of junction voltage respectively,
and are determined by the parameters CBD, CBS, CJ, CJSW, MJ, MJSW and PB.
.LP
There are two builtin models of the charge storage effects associated
with the thinoxide. The default is the piecewise linear voltagedependent
capacitance model proposed by Meyer. The second choice is the chargecontrolled
capacitance model of Ward and Dutton [1].
.LP
The XQC model parameter acts as a flag and a coefficient at the
same time. As the former it causes the program to use Meyer's model
whenever larger than 0.5 or not specified, and the chargecontrolled
model when between 0 and 0.5. In the latter case its value defines
the share of the channel charge associated with the drain terminal
in the saturation region.
.LP
The thinoxide charge storage effects are treated slightly different
for the LEVEL=1 model. These voltage dependent capacitances are
included only if TOX is specified in the input description and
they are represented using Meyer's formulation.
.LP
There is some overlap among the parameters describing the junctions,
e.g. the reverse current can be input either as IS (in A) or as
JS (in A/m**2). Whereas the first is an absolute value the second
is multiplied by AD and AS to give the reverse current of the drain
and source junctions respectively. This methodology has been chosen
since there is no sense in relating always junction characteristics
with AD and AS entered on the device card; the areas can be defaulted.
.LP
The same idea applies also to the zerobias junction capacitances
CBD and CBS (in F) on one hand, and CJ (in F/m**2) on the other.
.LP
The parasitic drain and source series resistance can be expressed
as either RD and RS (in ohms) or RSH (in ohms/sq.), the latter
being multiplied by the number of squares NRD and NRS input on the device card.
.LP
.SH
name parameter units default example
.LP
LEVEL model index 1
VTO zerobias threshold voltage V 0.0 1.0
KP transconductance parameter A/V**2 2.0E5 3.1E5
GAMMA bulk threshold parameter V**0.5 0.0 0.37
PHI surface potential V 0.6 0.65
LAMBDA channellength modulation
(MOS1 and MOS2 only) 1/V 0.0 0.02
RD drain ohmic resistance Ohm 0.0 1.0
RS source ohmic resistance Ohm 0.0 1.0
CBD zerobias BD junction
capacitance F 0.0 20FF
CBS zerobias BS junction
capacitance F 0.0 20FF
IS bulk junction saturation
current A 1.0E14 1.0E15
PB bulk junction potential V 0.8 0.87
CGSO gatesource overlap
capacitance per meter
channel width F/m 0.0 4.0E11
CGDO gatedrain overlap
capacitance per meter
channel width F/m 0.0 4.0E11
CGBO gatebulk overlap
capacitance per meter
channel length F/m 0.0 2.0E10
RSH drain and source diffusion
sheet resisitance Ohm/sq. 0.0 10.0
CJ zerobias bulk junction
bottom cap. per sqmeter
of junction area F/m**2 0.0 2.0E4
MJ bulk junction bottom
grading coef. 0.5 0.5
CJSW zerobias bulk junction
sidewall cap. per meter
of junction perimeter F/m 0.0 1.0E9
MJSW bulk junction sidewall
grading coef. 0.33
JS bulk junction saturation
current per sqmeter of
junction area A/m**2 1.0E8
TOX oxide thickness meter 1.0E7 1.0E7
NSUB substrate doping 1/cm**3 0.0 4.0E15
NSS surface state density 1/cm**2 0.0 1.0E10
NFS fast surface state density 1/cm**2 0.0 1.0E10
TPG type of gate material: 1.0
+1 opp. to substrate
1 same as substrate
0 Al gate
XJ metallurgical junction depth meter 0.0 1U
LD lateral diffusion meter 0.0 0.8U
UO surface mobility cm**2/Vs 600 700
UCRIT critical field for mobility
degradation (MOS2 only) V/cm 1.0E4 1.0E4
UEXP critical field exponent in
mobility degradation (MOS2 only) 0.0 0.1
UTRA transverse field coef (mobility)
(deleted for MOS2) 0.0 0.3
VMAX maximum drift velocity of
carriers m/s 0.0 5.0E4
NEFF total channel charge
(fixed and mobile) coefficient
(MOS2 only) 1.0 5.0
XQC thinoxide capacitance model
flag and coefficient of channel
charge share attributed to
drain (00.5) 1.0 0.4
KF flicker noise coefficient 0.0 1.0E26
AF flicker noise exponent 1.0 1.2
FC coefficient for forwardbias
depletion capacitance formula 0.5
DELTA width effect on threshold
voltage (MOS2 and MOS3) 0.0 1.0
THETA mobility modulation
(MOS3 only) 1/V 0.0 0.1
ETA static feedback (MOS3 only) 0.0 1.0
KAPPA saturation field factor (MOS3 only) 0.2 0.5
.LP
.NH 2
MESFET Models (both N and P channel)
.LP
The MESFET model is derived from the GaAs FET model of Statz et al. as
described in [6]. The d.c characteristics are defined by the parameters
VTO, B and BETA, which determine the variation of drain current with
gate voltage, ALPHA, which determines saturation voltage, and LAMBDA,
which determines the output conductance.
.LP
Two ohmic resistances, RD and RS, are included. Charge storage is modelled
by total gate charge as a function of gatedrain and gatesource voltages
and is defined by the parameters CGS, CGD and PB.
.LP
.SH
name parameter units default example
.LP
VTO pinchoff voltage V 2.0 2.0
BETA transconductance
parameter A/V**2 1e4 1e3
B doping tail extending
parameter 1/V 0.3 0.3
ALPHA saturation voltage parameter 1/V 2 2
LAMBDA channel length modulation
parameter 1/V 0 1e4
RD drain ohmic resistance ohms 0 100
RS source ohmic resistance ohms 0 100
CGS zerobias GS junction C F 0 5pF
CGD zerobias GD junction C F 0 1pF
PB gate junction potential V 1 0.6
KF flicker noise coefficient 0
AF flicker noise exponent 1
FC coefficient for forwardbias 0.5
depletion capacitance formula
.LP
[1] A. Vladimirescu and S. Liu, "The Simulation of MOS Integrated
Circuits Using SPICE2", ERL Memo No. ERL M80/7,Electronics Research
Laboratory, University of California, Berkeley, Oct. 1980.
.LP
.NH
SUBCIRCUITS
.LP
A subcircuit that consists of SPICE elements can be defined and
referenced in a fashion similar to device models.
.LP
The subcircuit is defined in the input file by a grouping of element
cards; the program then automatically inserts the group of elements
wherever the subcircuit is referenced.
.LP
There is no limit on the size or complexity of subcircuits, and
subcircuits may contain other subcircuits. An example of subcircuit
usage is given in Appendix A.
.LP
.NH 2
.SUBCKT Line
.LP
General form:
.LP
.SH
.SUBCKT subnam N1
.LP
Examples:
.LP
.SUBCKT OPAMP 1 2 3 4 39
.LP
A circuit definition is begun with a .SUBCKT card. SUBNAM is the
subcircuit name, and N1, N2, ... are the external
nodes, which cannot be zero. The group of element lines which immediately
follow the .SUBCKT line define the subcircuit. The last line in a
subcircuit definition is the .ENDS line (see below).
.LP
Control lines may not appear within a subcircuit definition; however,
subcircuit definitions may contain anything else, including other
subcircuit definitions, device models, and subcircuit calls (see below).
.LP
Note that any device models or subcircuit definitions included
as part of a subcircuit definition are strictly local (i.e., such
models and definitions are not known outside the subcircuit definition).
.LP
Also, any element nodes not included on the .SUBCKT line are strictly local,
with the exception of 0 (ground) which is always global.
.LP
.NH 2
.ENDS Line
.LP
General form:
.LP
.SH
.ENDS
.LP
Examples:
.LP
.ENDS OPAMP
.LP
This line must be the last one for any subcircuit definition. The
subcircuit name, if included, indicates which subcircuit definition
is being terminated; if omitted, all subcircuits 40 being defined
are terminated. The name is needed only when nested subcircuit
definitions are being made.
.LP
.NH 2
Subcircuit Calls
.LP
General form:
.LP
.SH
XYYYYYYY N1 SUBNAM
.LP
Examples:
.LP
X1 2 4 17 3 1 MULTI
.LP
Subcircuits are used in SPICE by specifying pseudoelements beginning
with the letter X, followed by the circuit nodes to be used in
expanding the subcircuit.
.LP
.NH
CONTROL LINES
.LP
.NH 2
.OPTIONS Line
.LP
General form:
.LP
.SH
.OPTIONS OPT1 OPT2 ... (or OPT=OPTVAL ...)
.LP
Examples:
.LP
.OPTIONS ACCT LIST NODE
.LP
This line allows the user to reset program control and user options
for specific simulation purposes. Any combination of the following
options may be included, in any order. 'x' (below) represents some
positive number.
.LP
.SH
option effect
.LP
GMIN=x resets the value of GMIN, the minimum conductance allowed by
the program. The default value is 1.0E12.
RELTOL=x resets the relative error tolerance of the program. The
default value is 0.001 (0.1 percent).
ABSTOL=x resets the absolute current error tolerance of the program.
The default value is 1 picoamp.
VNTOL=x resets the absolute voltage error tolerance of the program.
The default value is 1 microvolt.
TRTOL=x resets the transient error tolerance. The default value is
7.0 This parameter is an estimate of the factor by which
SPICE overestimates the actual truncation error.
CHGTOL=x resets the charge tolerance of the program. The default
value is 1.0E14.
PIVTOL=x resets the absolute minimum value for a matrix entry to be
accepted as a pivot. The default value is 1.0E13.
PIVREL=x resets the relative ratio between the largest column entry
and an acceptable pivot value. The default value is 1.0E3.
In the numerical pivoting algorithm the allowed minimum pivot
value is determined by EPSREL=AMAX1(PIVREL*MAXVAL,PIVTOL)
where MAXVAL is the maximum element in the column where a
pivot is sought (partial pivoting).
TNOM=x resets the nominal temperature. The default value is 27
deg C (300 deg K). TNOM can be overridden by a specification
on on any temperaturedependent device model.
ITL1=x resets the dc iteration limit. The default is 100.
ITL2=x resets the dc transfer curve iteration limit. The default is 50.
ITL5=x resets the transient analysis total iteration limit.
the default is 5000. Set ITL5=0 to omit this test.
DEFL=x resets the value for MOS channel length; the default is
100.0 micrometer.
DEFW=x resets the value for MOS channel width; the default is
100.0 micrometer.
DEFAD=x resets the value for MOS drain diffusion area;
the default is 0.0.
DEFAS=x resets the value for MOS source diffusion area;
the default is 0.0.
.LP
.NH 2
.DC Line
.LP
General form:
.LP
.SH
.DC SRCNAM VSTART VSTOP VINCR [SRC2 START2 STOP2 INCR2]
.LP
Examples:
.LP
.DC VIN 0.25 5.0 0.25
.DC VDS 0 10 .5 VGS 0 5 1
.DC VCE 0 10 .25 IB 0 10U 1U
.LP
This line defines the dc transfer curve source and sweep limits.
.LP
SRCNAM is the name of an independent voltage or current source.
VSTART, VSTOP, and VINCR are the starting, final, and incrementing
values respectively.
.LP
The first example will cause the value of the voltage source VIN
to be swept from 0.25 Volts to 5.0 Volts in increments of 0.25 Volts.
.LP
A second source (SRC2) may optionally be specified with associated
sweep parameters. In this case, the first source will be swept
over its range for each value of the second source.
.LP
This option can be useful for obtaining semiconductor device output
characteristics. See the second example data file in that section of the guide.
.LP
.NH 2
.NODESET Line
.LP
General form:
.LP
.SH
.NODESET V(NODNUM)=VAL V(NODNUM)=VAL ...
.LP
Examples:
.LP
.NODESET V(12)=4.5 V(4)=2.23
.LP
This line helps the program find the dc or initial transient solution
by making a preliminary pass with the specified nodes held to the
given voltages.
.LP
The restriction is then released and the iteration continues to
the true solution. The .NODESET line may be necessary for convergence
on bistable or astable circuits. In general, this line should not be necessary.
.LP
.NH 2
.IC Line
.LP
General form:
.LP
.SH
.IC V(NODNUM)=VAL V(NODNUM)=VAL ...
.LP
Examples:
.LP
.IC V(11)=5 V(4)=5 V(2)=2.2
.LP
This line is for setting transient initial conditions.
.LP
It has two different interpretations, depending on whether the UIC
parameter is specified on the .TRAN control line. Also, one should not
confuse this line with the .NODESET line.
.LP
The .NODESET line is only to help dc convergence, and does not affect final
bias solution (except for multistable circuits).
.LP
The two interpretations of this line are as follows:
.LP
1. When the UIC parameter is specified on the .TRAN line, then the node
voltages specified on the .IC line are used to compute the capacitor,
diode, BJT, JFET, and MOSFET initial conditions.
.LP
This is equivalent to specifying the IC=... parameter on each device
line, but is much more convenient. The IC=... parameter can still
be specified and will take precedence over the .IC values.
.LP
Since no dc bias (initial transient) solution is computed before
the transient analysis, one should take care to specify all dc
source voltages on the .IC line if they are to be used to compute
device initial conditions.
.LP
2. When the UIC parameter is not specified on the .TRAN line, the dc
bias (initial transient) solution will be computed before the transient
analysis. In this case, the node voltages specified on the .IC line will
be forced to the desired initial values during the bias solution.
.LP
During transient analysis, the constraint on these node voltages is removed.
This is the preferred method, since it allows SPICE to compute a consistent
dc solution.
.LP
.NH 2
.TF Line
.LP
General form:
.LP
.SH
.TF OUTVAR INSRC
.LP
Examples:
.LP
.TF V(5,3) VIN
.LP
.TF I(VLOAD) VIN
.LP
This line defines the smallsignal output and input for the dc
smallsignal analysis. OUTVAR is the smallsignal output variable
and INSRC is the smallsignal input source.
.LP
If this line is included, SPICE will compute the dc smallsignal
value of the transfer function (output/input), input resistance,
and output resistance.
.LP
For the first example, SPICE would compute the ratio of V(5,3)
to VIN, the smallsignal input resistance at VIN, and the smallsignal
output resistance measured across nodes 5 and 3.
.LP
.NH 2
.SENS Line
.LP
General form:
.LP
.SH
.SENS OV1
.LP
Examples:
.LP
.SENS V(9) V(4,3) V(17) I(VCC)
.LP
If a .SENS line is included in the input file, SPICE will determine the dc
smallsignal sensitivities of each specified output variable with
respect to every circuit parameter. Note: for large circuits, large
amounts of output can be generated.
.LP
.NH 2
.AC Line
.LP
General form:
.LP
.SH
.AC DEC ND FSTART FSTOP
.AC OCT NO FSTART FSTOP
.AC LIN NP FSTART FSTOP
.LP
Examples:
.LP
.AC DEC 10 1 10K
.AC DEC 10 1K 100MEG
.AC LIN 100 1 100HZ
.LP
DEC stands for decade variation, and ND is the number of points per decade.
.LP
OCT stands for octave variation, and NO is the number of points per octave.
.LP
LIN stands for linear variation, and NP is the number of points.
.LP
FSTART is the starting frequency, and FSTOP is the final frequency.
.LP
If this line is included in the file, SPICE will perform an ac
analysis of the circuit over the specified frequency range. Note
that in order for this analysis to be meaningful, at least one
independent source must have been specified with an ac value.
.LP
.NH 2
.DISTO Line
.LP
General form:
.LP
.SH
.DISTO DEC ND FSTART FSTOP
.DISTO OCT NO FSTART FSTOP
.DISTO LIN NP FSTART FSTOP
.LP
Examples:
.LP
.DISTO DEC 10 1kHz 100MHz
.DISTO DEC 10 1kHz 100MHz 0.9
.LP
This line does a smallsignal distortion analysis of the circuit.
.LP
A multidimensional Volterra series analysis is done using multidimensional
Taylor series to represent the nonlinearities at the operating
point. Terms of up to third order are used in the series expansion.
.LP
If the optional parameter F2OVERF1 is not specified, .DISTO does a
harmonic analysis  i.e, it analyses distortion in the circuit using
only a single input frequency F1, which is swept as specified by
arguments of the .DISTO command, exactly as in the .AC command.
.LP
Inputs at this frequency may be present at more than one input source,
and their magnitudes and phases are specified by the arguments of the DISTOF1
keyword in the input file lines for the input sources (see the
description of independent sources). The arguments of the DISTOF2
keyword are not relevant in this case.
.LP
The analysis produces information about about the AC values of all node
voltages and branch currents at the harmonic frequencies 2F1 and 3F1,
vs the input frequency F1 as it is swept.
.LP
A value of unity (as a complex distortion output) signifies:
cos(2PI(2F1).t) at 2F1 and
cos(2PI(3F1).t) at 3F1,
.LP
using the convention that unity at the fundamental frequency is
equivalent to cos(2PI(F1).t).
.LP
The distortion component desired  2F1 or 3F1  can be selected using
commands in Nutmeg, and then printed or plotted. Normally, one is
interested primarily in the magnitude of the harmonic components, so
the magnitude of the AC distortion value is looked at.
.LP
It should be noted that these are the AC values of the actual harmonic
components, and are NOT equal to HD2 and HD3. To obtain HD2 and HD3,
one must divide bt the corresponding values at F1, obtained from a .AC
line.
.LP
This division can be done using nutmeg commands.
.LP
If the optiional F2OVERF1 parameter is specified, it should be a real number
between (and not equal to) zero and unity. In this case, .DISTO does a
spectral analysis.
.LP
It considers the circuit with sinusoidal inputs, at two different frequencies,
F1 and F2. F1 is swept according to the .DISTO control line options,
exactly as in the .AC control line. F2 is kept fixed at a single frequency
as F1 sweeps: the value at which it is kept fixed is F2OVERF1 times FSTART.
.LP
Each independent source in the circuit may potentially have two (superimposed)
sinusoidal inputs for distortion, at the frequencies F1 and F2. The magnitude
and phase of the F1 component are specified by the arguments of the DISTOF1
keyword in the source's input line (see the description of independent
sources). The magnitude and phase of the F2 component are specified in the
arguments of the DISTOF2 keyword.
.LP
The analysis produces plots of all node voltages/branch currents in the
intermodulation product frequencies F1+F2, F1F2 and 2F1F2, vs the swept
frequency F1. The I.M product of interest may be selected using the
SETPLOT command and displayed with the print and plot commands.
.LP
It is to be noted that, as in the harmonic analysis case, the results are
the actual AC voltages and currents at the intermodulation frequencies,
and need to be normalised with respect to the .AC values to obtain the
IM parameters.
.LP
If the DISTOF1 or DISTOF2 keywords are missing from the description of an
independent source, then that source is assumed to have no input at the
corresponding frequency. The default values of the magnitude and phase
are unity and zero respectively. The phase should be specified in degrees.
.LP
It should be carefully noted that F2OVERF1 shoould ideally be an irrational
number and that, since this is not possible in practice, efforts should
be made to keep the denominator in its representation as large as possible 
certainly above 3  for accurate results.
.LP
In other words, if F2OVERF1 is represented as a fraction A/B, where A and B
are integers with no common factors, B should be as large as possible. Note
that A < B because F2OVERF1 is constrained to be < 1.
.LP
To illustrate why, consider the cases where F2OVERF1 is 49/100 and 1/2.
.LP
In a spectral analysis, the outputs produced are F1+F2, F1F2 and 2F1F2.
In the latter case, F1F2 = F2, so the result at the F1F2 component is
erroneous, because there is the strong F2 component at the same frequency.
.LP
Also, F1+F2 = 2F1F2 in the latter case, and each result is erroneous
individually. The problem is not there in the case F2OVERF1 = 49/100,
because F1F2 = 51/100.F1 != 49/100.F1 = F2. In this case, there are two
very closely spaced frequency components at F2 and F1F2.
.LP
One of the advantages of the Volterra series technique, is that it computes
distortions at mix frequencies expressed symbolically (i.e n.F1 +/ m.F2),
therefore, one is able to obtain the strengths of distortion components
accurately, even if the separation between them is very small, as opposed to
transient analysis, for example.
.LP
The disadvantage is, of course, that if two of the mix frequencies coincide,
the results are not merged together and presented (though this could,
presumably, be done as a postprocessing step. Currently, the interested user
should keep track of the mix frequencies personally, and add the distortions
at coinciding mix frequencies together, should it be necessary.
.LP
.NH 2
.NOISE Line
.LP
General form:
.LP
.SH
.NOISE OUTV INSRC DEC/OCT/LIN PTS FSTART FSTOP
+
.LP
Examples:
.LP
.NOISE V(5) VIN DEC 10 1kHz 100MHz
.NOISE V(5) V1 OCT 8 1.0 1.0E6 1
.LP
This line does a noise analysis of the circuit.
.LP
OUTV is the node at which the total output noise is desired.
.LP
INSRC is the name of the independent voltage or current source to which
noise is referred.
.LP
PTS FSTART FSTOP are .AC type parameters that specify the frequency
range over which plots are desired.
.LP
PTS_PER_SUMMARY is an optional integer. If specified, the noise
contributions of each noise generator is produced every PTS_PER_SUMMARY
frequency points.
.LP
The .NOISE control line produces two plots  one for the Noise Spectral
Density curves, and one for the Total Integrated Noise over the specified
frequency range. All noise voltages/currents are in squared units, (V**2/Hz
and A**2/Hz for spectral density, and V**2 and A**2 for integrated noise).
.LP
.NH 2
.TRAN Line
.LP
General form:
.LP
.SH
.TRAN TSTEP TSTOP >
.LP
Examples:
.LP
.TRAN 1NS 100NS
.TRAN 1NS 1000NS 500NS
.TRAN 10NS 1US UIC
.LP
TSTEP is the printing or plotting increment for lineprinter output.
For use with the postprocessor, TSTEP is the suggested computing increment.
.LP
TSTOP is the final time, and TSTART is the initial time. If TSTART
is omitted, it is assumed to be zero.
.LP
The transient analysis always begins at time zero.
.LP
In the interval , the circuit is analyzed (to reach
a steady state), but no outputs are stored. In the interval , the circuit is analyzed and outputs are stored.
.LP
TMAX is the maximum stepsize that SPICE will use (for default,
the program chooses either TSTEP or (TSTOPTSTART)/50.0, whichever
is smaller.
.LP
TMAX is useful when one wishes to guarantee a computing interval
which is smaller than the printer increment, TSTEP.
.LP
UIC (use initial conditions) is an optional keyword which indicates
that the user does not want SPICE to solve for the quiescent operating
point before beginning the transient analysis.
.LP
If this keyword is specified, SPICE uses the values specified using
IC=... on the various elements as the initial transient condition
and proceeds with the analysis.
.LP
If the .IC line has been specified, then the node voltages on the .IC
card are used to compute the intitial conditions for the devices. Look
at the description on the .IC line for its interpretation when UIC is not
specified.
.LP
.NH 2
.PZ Line
.LP
General Form:
.LP
.SH
.PZ NODE1 NODE2 NODE3 NODE4 CUR POL
.PZ NODE1 NODE2 NODE3 NODE4 CUR ZER
.PZ NODE1 NODE2 NODE3 NODE4 CUR PZ
.PZ NODE1 NODE2 NODE3 NODE4 VOL POL
.PZ NODE1 NODE2 NODE3 NODE4 VOL POL
.PZ NODE1 NODE2 NODE3 NODE4 VOL POL
.LP
Examples:
.LP
.PZ 1 0 3 0 CUR POL
.PZ 2 3 5 0 VOL ZER
.PZ 4 1 4 1 CUR PZ
.LP
CUR stands for a tranfer function of the type (output voltage)/(input current)
while VOL stands for a transfer function of the type (output voltage)/(input
voltage).
.LP
POL stands for pole analysis only, ZER for zero analysis only, and PZ for both.
.LP
This feature is provided mainly because if there is a nonconvergence in
finding poles or zeros, then at least the other may be found.
.LP
Finally, NODE1, and NODE2 are the two input nodes, and NODE3 and NODE4 are
the two output nodes. Thus, there is complete freedom regarding the output
and input ports and the type of transfer function. To print the results,
one should use the command PRINT PZ ALL.
.LP
.NH 2
.FOUR Line
.LP
General form:
.LP
.SH
.FOUR FREQ OV1
.LP
Examples:
.LP
.FOUR 100K V(5)
.LP
This line controls whether SPICE performs a Fourier analysis as
a part of the transient analysis.
.LP
FREQ is the fundamental frequency, and OV1, ..., are the output
variables for which the analysis is desired.
.LP
The Fourier analysis is performed over the interval , where TSTOP is the final time specified for the transient
analysis, and period is one period of the fundamental frequency.
The dc component and the first nine harmonics are determined.
.LP
For maximum accuracy, TMAX (see the .TRAN card) should be set to
period/100.0 (or less for very highQ circuits).
.LP
.NH 2
.PRINT Lines
.LP
General form:
.LP
.SH
.PRINT PRTYPE OV1
.LP
Examples:
.LP
.PRINT TRAN V(4) I(VIN)
.PRINT AC VM(4,2) VR(7) VP(8,3)
.PRINT DC V(2) I(VSRC) V(23,17)
.PRINT NOISE INOISE
.PRINT DISTO HD3 SIM2(DB)
.LP
This line defines the contents of a tabular listing of one to eight
output variables.
.LP
PRTYPE is the type of the analysis (DC, AC, TRAN, NOISE, or DISTO)
for which the specified outputs are desired.
.LP
The form for voltage or current output variables is as follows:
.LP
V(N1<,N2>)
.LP
specifies the voltage difference between nodes N1 and N2. If N2
(and the preceding comma) is omitted, ground (0) is assumed.
.LP
For the ac analysis, five additional outputs can be accessed by
replacing the letter V by:
.LP
VR  real part
VI  imaginary part
VM  magnitude
VP  phase
VDB  20*log10(magnitude)
.LP
I(VXXXXXXX) specifies the current flowing in the independent voltage
source named VXXXXXXX.
.LP
Positive current flows from the positive node, through the source,
to the negative node. For the ac analysis, the corresponding replacements
for the letter I may be made in the same way as described for voltage outputs.
.LP
Output variables for the noise and distortion analyses have a different
general form from that of the other analyses, i.e.
.LP
OV<(X)>
.LP
where OV is any of ONOISE (output noise), INOISE (equivalent input
noise), D2, HD3, SIM2, DIM2, or DIM3 (see description of distortion
analysis), and X may be any of:
.LP
R  real part
I  imaginary part
M  magnitude (default if nothing specified)
P  phase
DB  20*log10(magnitude)
.LP
thus, SIM2 (or SIM2(M)) describes the magnitude of the SIM2 dis
tortion measure, while HD2(R) describes the real part of the HD2
distortion measure. There is no limit on the number of .PRINT cards
for each type of analysis.
.LP
.NH 2
.PLOT Lines
.LP
General form:
.LP
.SH
.PLOT PLTYPE OV1 <(PLO1,PHI1)> ... OV8>
.LP
Examples:
.LP
.PLOT DC V(4) V(5) V(1)
.PLOT TRAN V(17,5) (2,5) I(VIN) V(17) (1,9)
.PLOT AC VM(5) VM(31,24) VDB(5) VP(5)
.PLOT DISTO HD2 HD3(R) SIM2
.PLOT TRAN V(5,3) V(4) (0,5) V(7) (0,10)
.LP
This line defines the contents of one plot of from one to eight
output variables.
.LP
PLTYPE is the type of analysis (DC, AC, TRAN, NOISE, or DISTO)
for which the specified outputs are desired.
.LP
The syntax for the OVI is identical to that for the .PRINT card,
described above.
.LP
The optional plot limits (PLO,PHI) may be specified after any of
the output variables. All output variables to the left of a pair
of plot limits (PLO,PHI) will be plotted using the same lower and
upper plot bounds. If plot limits are not specified, SPICE will
automatically determine the minimum and maximum values of all output
variables being plotted and scale the plot to fit. More than one
scale will be used if the output variable values warrant (i.e.,
mixing output variables with values which are ordersofmagnitude
different still gives readable plots). The overlap of two or more
traces on any plot is indicated by the letter X. When more than
one output variable appears on the same plot, the first variable
specified will be printed as well as plotted. If a printout of
all variables is desired, then a companion .PRINT line should be included.
There is no limit on the number of .PLOT lines specified for each type of analysis.
.LP
.NH
APPENDIX A: EXAMPLE DATA DECKS
.LP
.NH 2
Circuit 1
.LP
The following file determines the dc operating point and smallsignal
transfer function of a simple differential pair. In addition, the
ac smallsignal response is computed over the frequency range 1Hz to 100MEGHz.
.LP
.SH
SIMPLE DIFFERENTIAL PAIR
VCC 7 0 12
VEE 8 0 12
VIN 1 0 AC 1
RS1 1 2 1K
RS2 6 0 1K
Q1 3 2 4 MOD1
Q2 5 6 4 MOD1
RC1 7 3 10K
RC2 7 5 10K
RE 4 8 10K
.MODEL MOD1 NPN BF=50 VAF=50 IS=1.E12 RB=100
+ CJC=.5PF TF=.6NS
.TF V(5) VIN
.AC DEC 10 1 100MEG
.PLOT AC VM(5) VP(5)
.PRINT AC VM(5) VP(5)
.END
.LP
.NH 2
Circuit 2
.LP
The following file computes the output characteristics of a MOSFET
device over the range 010V for VDS and 05V for VGS.
.LP
.SH
MOS OUTPUT CHARACTERISTICS
.OPTIONS NODE NOPAGE
VDS 3 0
VGS 2 0
M1 1 2 0 0 MOD1 L=4U W=6U AD=10P AS=10P 59
.MODEL MOD1 NMOS VTO=2 NSUB=1.0E15 UO=550
* VIDS MEASURES ID, WE COULD HAVE USED VDS,
* BUT ID WOULD BE NEGATIVE
VIDS 3 1
.DC VDS 0 10 .5
VGS 0 5 1
.PRINT DC I(VIDS) V(2)
.PLOT DC I(VIDS)
.END
.LP
.LP
.NH 2
Circuit 3
.LP
The following file determines the dc transfer curve and the transient
pulse response of a simple RTL inverter. The input is a pulse from
0 to 5 Volts with delay, rise, and fall times of 2ns and a pulse
width of 30ns. The transient interval is 0 to 100ns, with printing
to be done every nanosecond.
.LP
.SH
SIMPLE RTL INVERTER
VCC 4 0 5
VIN 1 0 PULSE 0 5 2NS 2NS 2NS 30NS
RB 1 2 10K
Q1 3 2 0 Q1
RC 3 4 1K
.PLOT DC V(3)
.PLOT TRAN V(3) (0,5)
.PRINT TRAN V(3)
.MODEL Q1 NPN BF 20 RB 100 TF .1NS CJC 2PF
.DC VIN 0 5 0.1
.TRAN 1NS 100NS
.END
.LP
.LP
.NH 2
Circuit 4
.LP
The following file simulates a fourbit binary adder, using several
subcircuits to describe various pieces of the overall circuit.
.LP
.SH
ADDER  4 BIT ALLNANDGATE BINARY ADDER
.LP
*** SUBCIRCUIT DEFINITIONS
.SUBCKT NAND 1 2 3 4
* NODES: INPUT(2), OUTPUT, VCC
Q1 9 5 1 QMOD
D1CLAMP 0 1 DMOD
Q2 9 5 2 QMOD
D2CLAMP 0 2 DMOD
RB 4 5 4K
R1 4 6 1.6K
Q3 6 9 8 QMOD
R2 8 0 1K
RC 4 7 130
Q4 7 6 10 QMOD
DVBEDROP 10 3 DMOD
Q5 3 8 0 QMOD
.ENDS NAND
.LP
.SUBCKT ONEBIT 1 2 3 4 5 6
* NODES: INPUT(2), CARRYIN, OUTPUT, CARRYOUT, VCC
X1 1 2 7 6 NAND
X2 1 7 8 6 NAND
X3 2 7 9 6 NAND
X4 8 9 10 6 NAND
X5 3 10 11 6 NAND
X6 3 11 12 6 NAND
X7 10 11 13 6 NAND
X8 12 13 4 6 NAND
X9 11 7 5 6 NAND
.ENDS ONEBIT
.LP
.SUBCKT TWOBIT 1 2 3 4 5 6 7 8 9
* NODES: INPUT  BIT0(2) / BIT1(2), OUTPUT  BIT0 / BIT1,
* CARRYIN, CARRYOUT, VCC
X1 1 2 7 5 10 9 ONEBIT
X2 3 4 10 6 8 9 ONEBIT
.ENDS TWOBIT
.LP
.SUBCKT FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
* NODES: INPUT  BIT0(2) / BIT1(2) / BIT2(2) / BIT3(2),
* OUTPUTBIT0/BIT1/BIT2/BIT3, CARRYIN, CARRYOUT, VCC
X1 1 2 3 4 9 10 13 16 15 TWOBIT
X2 5 6 7 8 11 12 16 14 15 TWOBIT
.ENDS FOURBIT
.LP
*** DEFINE NOMINAL CIRCUIT
.MODEL DMOD D
.MODEL QMOD NPN(BF=75 RB=100 CJE=1PF CJC=3PF)
VCC 99 0 DC 5V
VIN1A 1 0 PULSE(0 3 0 10NS 10NS 10NS 50NS)
VIN1B 2 0 PULSE(0 3 0 10NS 10NS 20NS 100NS)
VIN2A 3 0 PULSE(0 3 0 10NS 10NS 40NS 200NS)
VIN2B 4 0 PULSE(0 3 0 10NS 10NS 80NS 400NS)
VIN3A 5 0 PULSE(0 3 0 10NS 10NS 160NS 800NS)
VIN3B 6 0 PULSE(0 3 0 10NS 10NS 320NS 1600NS)
VIN4A 7 0 PULSE(0 3 0 10NS 10NS 640NS 3200NS)
VIN4B 8 0 PULSE(0 3 0 10NS 10NS 1280NS 6400NS)
X1 1 2 3 4 5 6 7 8 9 10 11 12 0 13 99 FOURBIT
RBIT0 9 0 1K
RBIT1 10 0 1K
RBIT2 11 0 1K
RBIT3 12 0 1K
RCOUT 13 0 1K
.PLOT TRAN V(1) V(2) V(3) V(4) V(5) V(6) V(7) V(8)
.PLOT TRAN V(9) V(10) V(11) V(12) V(13)
.PRINT TRAN V(1) V(2) V(3) V(4) V(5) V(6) V(7) V(8)
.PRINT TRAN V(9) V(10) V(11) V(12) V(13)
.LP
*** (FOR THOSE WITH MONEY (AND MEMORY) TO BURN)
.TRAN 1NS 6400NS
.OPTIONS ACCT LIST NODE LIMPTS=6401
.END
.LP
.NH 2
Circuit 5
.LP
The following file simulates a transmissionline inverter. Two
transmissionline elements are required since two propagation modes
are excited. In the case of a coaxial line, the first line (T1)
models the inner conductor with respect to the shield, and the
second line (T2) models the shield with respect to the out side world.
.LP
.SH
TRANSMISSIONLINE INVERTER
V1 1 0 PULSE(0 1 0 0.1N)
R1 1 2 50
X1 2 0 0 4 TLINE
R2 4 0 50
.SUBCKT TLINE 1 2 3 4
T1 1 2 3 4 Z0=50 TD=1.5NS
T2 2 0 4 0 Z0=100 TD=1NS
.ENDS TLINE
.TRAN 0.1NS 20NS
.PLOT TRAN V(2) V(4)
.END
.LP
.NH
APPENDIX C: BIPOLAR MODEL EQUATIONS
.LP
(G terms omitted)
min
.LP
Acknowledgment:
.LP
This section has been contributed by Bill Bidermann at HP labs.
.LP
.NH 2
D.C. MODEL
.LP
qVB'E' qVB'C' qVB'C' qVB'C'
   
IS NF*kT NR*kT IS NR*kT NC*kT
IC = (e  e )   ( e 1)  ISC( e 1)
QB BR
.LP
.LP
qVB'E' qVB'C' qVB'E' qVB'C'
IS NF*kT IS NR*kT NE*kT NC*kT
IB =  (e 1) +  (e 1) + ISE(e 1) + ISC(e 1)
BF BR
.LP
NOTE: The last two terms in the expression of the base current
IB represent the components due to recombination in the BE and
BC space charge regions at low injection.
.LP
If IRB not specified
.LP
RBRBM
RBB' = RBM + 
QB
.LP
If IRB specified
.LP
TAN(Z)Z
RBB' = 3(RBRB *  + RBM
Z*TAN(Z)*TAN(Z)
.LP
Where:
.LP
1+(144IB/(pi*pi*IRB)+1)**0.5
Z = 
24/(pi*pi)*(IB/IRB)**0.5
.LP
Q1
QB =  (1+(1+4Q2)**0.5)
2
.LP
1
_____________
.LP
Q1 = VB'C' VB'E'
1    
VAF VAR
.LP
qVB'E' qVB'C'
IS  
 NF*kT IS NR*kT
Q2 = IKF (e 1) +  (e 1)
IKR
.LP
NOTE: IRB is the current where the base resistance falls halfway
to its minimum value. VAF and VAR are forward and reverse Early
voltages respectively. IKF and IKR determine the high current beta
rolloff with IC. ISE, ISC, NE and NC determine the low current
beta rolloff with IC.
.LP
.NH 2
A.C. MODEL
.LP
qVB'E'
d IS NF*kT VB'E'
CBE =  (TFF*  (e 1)) + CJE(1 )  MJ
d VB'E' QB VJE
.LP
Where:
.LP
VB'C'

2 1.44VTF
TFF = TF ( 1 + XTF * (IF/(IF+ITF)) * e )
.LP
qVB'E'

NF*kT
IF = IS( e 1)
.LP
CB1 = CBC*(1XCJC)
.LP
CB2 = CBC * XCJC
.LP
qVB'C'

qIS kT VB'C' MJC
CBC = TR (  e ) + CJC (1   )
NR*kT VJC
.LP
VC'S' MJS
CSS = CJS(1   )
VJS
.LP
NOTE: all junction capacitances of the form V M
C0*(1  )
phi
.LP
revert to the form
.LP
M*(VFC*phi)
C0/((1FC)**M) * (1 +  )
phi(1FC)
.LP
when V > FC*phi ( For CSS assumes FC = 0 )
.LP
.NH 2
NOISE MODEL
.LP
4kT
2 
IRBB' = RBB' DELTA f



4kT 
2 ___ 
IRC = RC DELTA f  Thermal noise



4kT  KF*IB**AF
2  _________
IRE = 2REB DELTA f+ f DELTA f
.LP
Note: The first term is shot noise and the second term is flicker noise.
.LP
2
ICN = 2qIC DELTA f
.LP
Note: This is shot noise.
.LP
.NH 2
TEMPERATURE EFFECTS
.LP
All junctions have dependences identical to the diode model but
all N factors are considered equal 1.
.LP
T
BF and BR go as () XTB
TNOM
.LP
when NF=1.This is done through appropriate changes in BF , BR and
ISE, ISC according to the following equations respectively:
.LP
T
 * XTB
BF' (or BR') = BF (or BR) * (TNOM)
.LP
qEG TTNOM
 
T (XTIXTB) Nk T*TNOM
ISE' (or ISC') = ISE (or ISC) *(  ) * e
TNOM
.LP
.NH 2
EXCESS PHASE
.LP
This is a delay (linear phase) in the gm generator in AC analysis.
It is also used in transient analysis using a Bessel polynomial
approximation. Excess phase, PTF, is specified as the number of
extra degrees of phase at the frequency
.LP
1
f =  Hertz
2piTF
.LP
.NH
APPENDIX D:
.LP
.ALTER STATEMENT AND THE SOURCESTEPPING METHOD
.LP
.LP
The .ALTER statement allows SPICE to run with altered circuit parameters.
.LP
.LP
General form:
.LP
.SH
.ALTER ELEMENT LINES (DEVICE LINES, MODEL LINES) .ALTER (or .END LINE)
.LP
.LP
.LP
.SH
Examples:
R1 1 0 5K
VCC 3 0 10
M1 3 2 0 MOD1 L=5U W=2U
.MODEL MOD1 NMOS(VTO=1.0 KP=2.0E5 PHI=0.6 NSUB=2.0E15
+TOX=0.1U)
.ALTER
R1 1 0 3.5K
VCC 3 0 12
M1 3 2 0 MOD1 L=10U W=2U
.MODEL MOD1 NMOS(VTO=1.2 KP=2.0E5 PHI=0.6 NSUB=5.0E15
+TOX=1.5U)
.ALTER
M1 3 2 0 MOD1 L=10U W=4U
.END
.LP
.LP
.LP
This line introduces the element(s), device(s) and model(s) whose
parameters are changed during the execution of the input file.
.LP
The analyses specified in the file will start over again with the
changed parameters. The .ALTER line with the lines defining the new
parameters should be placed just before the .END card.
.LP
The syntax for the element (device, model) lines is identical to
that of the lines with the original parameters. There is no limit
on the number of .ALTER lines and the circuit will be reanalyzed as many
times as the number of .ALTER cards. Subsequent .ALTER operations employ
parameters of the previous change. No topological change of the circuit is
allowed.
.LP
.LP
.SH
The sourcestepping method
.LP
can enhance DC convergence. But it is slower than direct use of
the NewtonRaphson method. Therefore it is best used as an alternative
to achieve convergence of DC operating point when the circuit fails
to converge by using the NewtonRaphson method.
.LP
The sourcestepping method is used by SPICE when the variable ITL6 in
the .OPTIONS line is set to the iteration limit at each step of the
source(s). For example,
.LP
.SH
.OPTIONS ITL6=30
.LP
.LP
will cause SPICE to use sourcestepping method with iteration limit
30 at each step.
.LP
By default, ITL6 is 0 which means to use the NewtonRaphson method directly.
