VSPICE3 ANALOG DESIGN TOOLKIT
HIERARCHICAL SCHEMATIC CAPTURE
All drawings are fully compatible with Cadence/Valid G.E.D format.
Analog primitives are selected from a menu, to speed the design process, and facilities exist for cut-and-paste from one drawing to another, and for group move, delete and copy on the same drawing.
The drawing may be freely annotated, and on-screen text can be edited. Hardcopy is to a PostScript laser printer, or to a Hewlett-Packard pen plotter.
To eliminate the need for writing subcircuit definitions, schematics are constructed hierarchically. Instead of subcircuits, components are modelled by real circuits, with easily generated custom symbols. The user-transparent high speed netlister flattens the hierarchy into a single netlist, which simulates faster than one containing subcircuits.
To minimize circuit errors, a CHECK function is included, which will highlight open wires, open pins, missing properties and erroneous properties. It also issues a warning if a ground symbol is missing from the schematic.
UNLIMITED SEMICONDUCTOR MODELS
No matter how comprehensive a library may be, it may still miss the very device needed for a particular project. Vspice3 comes with a standard library of around a thousand devices and, additionally, a library generation tool, Vmodel. With Vmodel, any semiconductor device can be modelled from its data sheet parameters, or from simple measurements, if the data sheet is inadequate, or not available.
Additionally, any operational amplifier having a single-pole roll-off characteristic can be modelled by inputting its data sheet parameters. The model created is in the form of a schematic, which the user can read and modify.
The stimulus may be defined in two ways. The experienced SPICE user can define it by its SPICE syntax, while the new user can generate it interactively while viewing the effects of parameter changes on the graphically displayed waveform. When the waveform is satisfactory, it can be attached to the appropriate point on the schematic. The stimulus is entered into the netlist, but not on the schematic, to avoid making changes to what might be an engineering drawing.
Test circuits are provided for the plotting of common semiconductor characteristics. These include output characteristics, forward beta versus collector current, forward beta versus frequency, and the equivalent MOSFET/JFET characteristics.
ANALOG BEHAVIOURAL MODELLING
Models are created as equivalent circuits, using traditional analog circuit design techniques. The transfer functions of voltage and current sources can be defined by any equation composed of the following functions:
+ - * / ^ abs asinh cosh sin acos atan exp sinh acosh atanh ln sqrt asin cos log tan
The above functions can apply to any combination of circuit voltages or currents.
Additionally, the standard SPICE sum of the terms of a polynomial up to the 20th power can be used.
GRAPHICAL WAVEFORM ANALYSIS
In addition to the simple functions, like add, subtract, multiply, divide and invert, waveforms can be differentiated and integrated. The resulting waveform can be saved, possibly for use in further calculation. High level mathematical operations include forward and inverse Fast Fourier Transforms (with a choice of 4 windowing functions, and zero filling to 16k points), convolution, deconvolution, and auto and cross correlation.
A specialist function is for the calculation and display of reflection damping coefficient from plots of transmission system impedance against frequency.
All operations are performed in complex double-precision arithmetic, and can accept floating point constants as one argument.
Any complex waveforms can be displayed in the complex plane, and any two waveforms can be plotted against each other, in an X-Y plot.
Up to 40 waveforms can be displayed at one time, and any or all can be dumped to an ASCII file.
Waveform data in ASCII files can be read in and displayed, or used as stimulus in a simulation. This provides a convenient link to the real world, as most digital storage scopes and network analysers have an ASCII dump facility.
SUPERIOR TRANSIENT ANALYSIS
The timestep control mechanism used in Spice3D2 transient analysis is completely different to that used in SPICE based simulators. It offers better convergence in most cases, and eliminates the need for the user to reset the values of ITL3 and ITL4.
To further minimize user-intervention, the simulator will automatically switch first to the source-stepping method, and next to GMIN stepping, if the Newton-Raphson iteration method fails, thus providing two further levels of convergence assist.
A pole-zero analysis can be performed of any two-port network, even if the transfer function is unknown. This analysis gives a graphical display of the pole-zero positions in the complex plane and, additionally, prints the values to six decimal places.
1. GaAs FET
The model provided is that due to H. Statz et al. in IEEE Trans. on Electron Devices, V34 No 2, Feb 1987, and is probably the most accurate one, since it includes improvements not found in earlier models.
2. Silicon Resistors and Capacitors
When designing integrated circuits, it is more accurate to describe these components in terms of their dimensions, than to use lumped values. Particularly with capacitors, where the effect of sidewall capacitance needs to be taken into account, or with resistors, where narrowing due to side-etching is defined.
3. Uniform Distributed RC Lines
The ideal transmission lines available with most versions of SPICE suffer from several well-known problems. The Gertzberg model provides a more versatile model, which includes losses and simulates more accurately. The line can be defined either in terms of capacitors or of reverse-biased PN junctions, with voltage-variable capacitance and optional internal resistance.
Both voltage and current controlled switches can be simulated, with positive or negative hysteresis and on/off resistance specified. These devices add a new perspective to the modelling of devices such as logic functions or data converters. Also, since an open switch looks like a current source, while a closed switch looks like a voltage source, the simulation of relays driving long lines can be done more accurately than by other means.
5. Berkeley Short Channel IGFET Model (BSIM)
The latest (1990) models of MOS transistors, from Level 1 to Level 6, are included. The BSIM (Level 4) model is that due to Min Chie Jeng, ERL Memo M90/90 Electronics Research Laboratory, University of California Berkeley, October 1990. The Level 5 model is BSIM2, as described in the same paper, while Level 6 is that due to Sakurai and Newton, ERL Memo 90/19 Berkeley, March 1990.
SIMULATION OF MECHANICAL COMPONENTS
Motors, gearboxes and rotating loads are readily modelled and simulated, providing outputs of torque and angular velocity.
The models can be used to predict vibration, stability and positioning errors of steerable antenna systems, power generation equipment, or any other type of open or closed loop servo system.
Since both time and frequency domain analyses are available, loop phase and gain is easily established, and Pole-Zero analysis gives valuable information about potential problems.
Using the well-established Pei and Lauritzen model, a library of around 500 popular magnetic materials is supplied, together with application circuits of ferro-resonant regulator, Royer oscillator, half-bridge converter, and switched-mode power supply. A software routine makes core modelling easy by generating model parameters from the core magnetic characteristics input by the user. Additionally, switched-mode power supply modelling techniques established by Dr Vincent Bello give a means of designing and testing these supplies far superior to the traditional 'brute force' methods.
LAPLACE TRANSFER FUNCTION SIMULATION
The ultimate Analog High-Level Descriptive Language is the transfer function.
Vspice3 includes a modular approach to the simulation of any system, electronic, electromechanical, or mechanical, which can be described by an s-domain transfer function, of any order.
The transfer function can be simulated in conjunction with conventional components, such as diodes, transistors, etc, so that a system can be literally designed 'top down bottom up'.
One major advantage of this method of simulation is that, unlike a pure Laplace transfer function, which assumes a linear system, limiting can be simulated of any part of the function, by merely using a diode clamp with the appropriate voltage.
The models are suitable for AC, DC and Transient analysis, and an impulse or step response can be easily obtained. This can be used, in conjunction with the on-line convolution function, to gauge the effect of a complex system on any waveform.
When used together with the Pole-Zero analysis, this facility gives a greater insight into a system's performance than can be obtained by conventional analysis methods.
1. Nroff to PostScript Converter
2. Finite Impulse Response Filter coefficient calculator
3. Time domain and frequency domain waveform generators
4. SPICE capacitor Meyer function exponent and CJO calculator
5. SPICE netlist to graphical drawing converter