Or, by electronic mail to:

spice@Berkeley.EDU (Internet) ucbvax!spice (UUCP-net)

Please include input to the program, output, suggestion as to where the problem may be and, if possible, a suggested fix.

SPICE is a general-purpose circuit simulation program for nonlinear dc, nonlinear transient, and linear ac analyses. Circuits may contain resistors, capacitors, inductors, mutual inductors, independent voltage and current sources, four types of dependent sources, lossless transmission lines, switches, uniform distributed RC lines, and the five most common semiconductor devices: diodes, BJT's, JFET's, MESFET's and MOSFET's.

The SPICE3 version is based directly on SPICE2G6. While SPICE3 is being developed to include new features, it continues to support those capabilities and models which remain in extensive use in the SPICE2 program.

SPICE has built-in models for the semiconductor devices, and the user need specify only the pertinent model parameter values. The model for the BJT is based on the integral charge model of Gummel and Poon; however, if the Gummel-Poon parameters are not specified, the model reduces to the simpler Ebers-Moll model. In either case, charge storage effects, ohmic resistances, and a current-dependent output conductance may be included. The diode model can be used for either junction diodes or Schottky barrier diodes. The JFET model is based on the FET model of Shichman and Hodges. Six MOSFET models are implemented; MOS1 is described by a square-law I-V characteristic MOS2 is an analytical model while MOS3 is a semi-empirical model. MOS6 is a simple analytic model accurate in the short channel region; MOS4 and MOS5 are the BSIM (Berkeley Short-channel IGFET Model) and BSIM2, MOS2, MOS3 and MOS4 include second-order effects such as channel-length modulation, subthreshold conduction, scattering-limited velocity modulation, small-size effects, and charge-controlled capacitances.

.NH TYPES OF ANALYSIS

.NH 2 DC Analysis

The dc analysis portion of SPICE determines the dc operating point of the circuit with inductors shorted and capacitors opened. The dc analysis options are specified on the .DC, .TF and .OP, control lines. A dc analysis is automatically performed prior to a transient analysis to determine the transient initial conditions, and prior to an ac small-signal analysis to determine the linearized, small-signal models for nonlinear devices.

If requested, the dc small-signal value of a transfer function (ratio of output variable to input source), input resistance, and output resistance will also be computed as a part of the dc solution.

The dc analysis can also be used to generate dc transfer curves: a specified independent voltage or current source is stepped over a user-specified range and the dc output variables are stored for each sequential source value.

.NH 2 AC Small-Signal Analysis

The ac small-signal portion of SPICE computes the ac output variables as a function of frequency.

The program first computes the dc operating point of the circuit and determines linearized, small-signal models for all of the nonlinear devices in the circuit.

The resultant linear circuit is then analyzed over a user-specified range of frequencies. The desired output of an ac small-signal analysis is usually a transfer function (voltage gain, transimpedance, etc).

If the circuit has only one ac input, it is convenient to set that input to unity and zero phase, so that output variables have the same value as the transfer function of the output variable with respect to the input.

.NH 2 Noise Analysis

The noise analysis portion of SPICE does analysis of device-generated noise for the given circuit. When provided with an input source and an output port, the analysis calculates the noise contributions of each device (and each noise generator within the device) to the output port voltage. It also calculates the input noise to the circuit, equivalent to the output noise referred to the specified input source. This is done for every frequency point in the specified range - the calculated value of the noise corresponds to the spectral density of the circuit variable viewed as a stationary gaussian stochastic process.

After calculating the spectral densities, noise analysis integrates these values over the specified frequency range to arrive at a total noise voltage/current (over this frequency range). This calculated value corresponds to the variance of the circuit variable, viewed as a stationary gaussian process.

.NH 2 Transient Analysis

The transient analysis portion of SPICE computes the transient output variables as a function of time over a user-specified time interval.

The initial conditions are automatically determined by a dc analysis. All sources which are not time dependent (for example, power supplies) are set to their dc value. The transient time interval is specified on a .TRAN control line.

.NH 2 Pole-Zero Analysis

The pole-zero analysis portion of SPICE computes the poles and/or zeros in the small-signal ac transfer function. The program first computes the d.c operating point, and then determines the linearised small-signal models for all the nonlinear devices in the circuit. This circuit is then used to find the poles and zeros of the transfer function.

Two types of transfer functions are allowed: one, of the form: (output voltage) / (input voltage)

and the other, of the form: (output voltage) / (input current);

These two types of transfer functions cover all the cases, and one can find the poles/zeros of functions like input/output impedances and voltage gain.

The input and output ports are specified as two pairs of nodes.

The pole zero analysis works with resistors, capacitors, inductors, linear controlled sources, BJT's, MOSFET's, JFET's and diodes. Transmission lines are not supported.

.NH 2 Small-signal Distortion Analysis

The distortion analysis portion of SPICE computes steady-state harmonic and intermodulation products for small input signal magnitudes. If signals of a single frequency are specified as the input to the circuit, the complex values of the second and third harmonics are determined at every point in the circuit. If there are signals of two frequencies input to the circuit, the analysis finds out the complex values of the circuit variables at the sum and difference of the input frequencies, and at the difference of the smaller frequency from the second harmonic of the larger frequency.

Distortion analysis is supported for the following devices: diode, BJT, JFET, MOSFET's (levels 1, 2, 3 and BSIM) and MESFET's. All linear devices are automatically supported by distortion analysis. If there are switches present in the circuit, the analysis continues to be accurate, provided the switches do not change state under the small excitations used for distortion calculation.

.NH 2 Analysis at Different Temperatures

All input data for SPICE is assumed to have been measured at 27 deg C (300 deg K), which can be changed by use of the TNOM parameter on the .OPTION control line. This value can further be overridden for any device which models temperature effects by specifying the TNOM parameter on the model itself. The circuit simulation is performed at a temperature of 27 deg C, unless overridden by a TEMP parameter on the .OPTION control line. Individual instances may further override the circuit temperature through the specification of a TEMP parameter on the instance.

Temperature appears explicitly in the exponential terms of the BJT and diode model equations. In addition, saturation currents have a built-in temperature dependence. The temperature dependence of the saturation current in the BJT models is determined by:

IS(T1) = IS(T0)*((T1/T0)**XTI)*exp(q*EG*(T1-T0)/(k*T1*T0))

where k is Boltzmann's constant, q is the electronic charge, EG is the energy gap which is a model parameter, and XTI is the saturation current temperature exponent (also a model parameter, and usually equal to 3).

The temperature dependence of forward and reverse beta is according to the formula:

beta(T1)=beta(T0)*(T1/T0)**XTB

where T1 and T0 are in degrees Kelvin, and XTB is a user-supplied model parameter. Temperature effects on beta are carried out by appropriate adjustment to the values of BF, ISE, BR, and ISC.

Temperature dependence of the saturation current in the junction diode model is determined by:

IS(T1) = IS(T0)*((T1/T0)**(XTI/N))*exp(q*EG*(T1-T0)/(k*N*T1*T0))

where N is the emission coefficient, which is a model parameter, and the other symbols have the same meaning as above. Note that for Schottky barrier diodes, the value of the saturation current temperature exponent, XTI, is usually 2. Temperature appears explicitly in the value of junction potential, PHI, for all the device models. The temperature dependence is determined by:

PHI(TEMP) = k*TEMP/q*log(Na*Nd/Ni(TEMP)**2)

where k is Boltzmann's constant, q is the electronic charge, Na is the acceptor impurity density, Nd is the donor impurity density, Ni is the intrinsic concentration, and EG is the energy gap.

Temperature appears explicitly in the value of surface mobility, UO, for the MOSFET model. The temperature dependence is determined by:

UO(TEMP) = UO(TNOM)/(TEMP/TNOM)**(1.5)

The effects of temperature on resistors is modeled by the formula:

value(TEMP) = value(TNOM)*(1+TC1*(TEMP-TNOM)+TC2*(TEMP-TNOM)**2))

where TEMP is the circuit temperature, TNOM is the nominal temperature, and TC1 and TC2 are the first- and second-order temperature coefficients. .NH CONVERGENCE

Both dc and transient solutions are obtained by an iterative process which is terminated when both of the following conditions hold:

1) The nonlinear branch currents converge to within a tolerance of 0.1 percent or 1 picoamp (1.0E-12 Amp), whichever is larger.

2) The node voltages converge to within a tolerance of 0.1 percent or 1 microvolt (1.0E-6 Volt), whichever is larger.

Although the algorithm used in SPICE has been found to be very reliable, in some cases it will fail to converge to a solution. When this failure occurs, the program terminates the job.

Failure to converge in the dc analysis is usually due to an error in specifying circuit connections, element values, or model parameter values.

Regenerative switching circuits or circuits with positive feedback probably will not converge in the dc analysis unless the OFF option is used for some of the devices in the feedback path, or the .NODESET control line is used to force the circuit to converge to the desired state.

.NH INPUT FORMAT

The input format for SPICE is of the free format type. Fields on a line are separated by one or more blanks, a comma, an equal (=) sign, or a left or right parenthesis; extra spaces are ignored. A line may be continued by entering a + (plus) in column 1 of the following card; SPICE continues reading beginning with column 2.

A name field must begin with a letter (A through Z) and cannot contain any delimiters. Only the first eight characters of the name are used.

A number field may be an integer field (12, -44), a floating point field (3.14159), either an integer or floating point number followed by an integer exponent (1E-14, 2.65E3), or either an integer or a floating point number followed by one of the following scale factors:

T=1E12 G=1E9 MEG=1E6 K=1E3 MIL=25.4E-6

M=1E-3 U=1E-6 N=1E-9 P=1E-12 F=1E-15

Letters immediately following a number that are not scale factors are ignored, and letters immediately following a scale factor are ignored. Hence, 10, 10V, 10VOLTS, and 10HZ all represent the same number, and M, MA, MSEC, and MMHOS all represent the same scale factor.

Note that 1000, 1000.0, 1000HZ, 1E3, 1.0E3, 1KHZ, and 1K all represent the same number.

.NH CIRCUIT DESCRIPTION

The circuit to be analyzed is described to SPICE by a set of element lines, which define the circuit topology and element values, and a set of control lines, which define the model parameters and the run controls.

The first line in the input file must be the title, and the last line must be ".END". The order of the remaining cards is arbitrary (except, of course, that continuation lines must immediately follow the line being continued).

Each element in the circuit is specified by an element line that contains the element name, the circuit nodes to which the element is connected, and the values of the parameters that determine the electrical characteristics of the element. The first letter of the element name specifies the element type. The format for the SPICE element types is given in what follows.

The strings XXXXXXX, YYYYYYY, and ZZZZZZZ denote arbitrary alphanumeric strings. For example, a resistor name must begin with the letter R and can contain from one to eight characters. Hence, R, R1, RSE, ROUT, and R3AC2ZY are valid resistor names.

Data fields that are enclosed in lt and gt signs '< >' are optional.

All indicated punctuation (parentheses, equal signs, etc.) are required.

With respect to branch voltages and currents, SPICE uniformly uses the associated reference convention (current flows in the direction of voltage drop).

Nodes must be nonnegative integers but need not be numbered sequentially. The datum (ground) node must be numbered zero.

The circuit cannot contain a loop of voltage sources and/or inductors and cannot contain a cutset of current sources and/or capacitors.

Each node in the circuit must have a dc path to ground.

Every node must have at least two connections except for transmission line nodes (to permit unterminated transmission lines) and MOSFET substrate nodes (which have two internal connections anyway).

.NH TITLE LINE, COMMENT LINES AND .END LINE

.NH 2 Title Line

Examples:

POWER AMPLIFIER CIRCUIT

TEST OF CAM CELL

This line must be the first line in the input file. Its contents are printed verbatim as the heading for each section of output.

.NH 2 .END Line

Examples:

.END

This line must always be the last line in the input file. Note that the period is an integral part of the name.

.NH 2 Comment Line

General Form:

*

Examples:

* RF=1K GAIN SHOULD BE 100

* MAY THE FORCE BE WITH MY CIRCUIT

The asterisk in the first column indicates that this line is a comment card. Comment lines may be placed anywhere in the circuit description.

.NH ELEMENT LINES

.NH 2 Resistors

General form:

RXXXXXXX N1 N2 VALUE

Examples:

R1 1 2 100 RC1 12 17 1K

N1 and N2 are the two element nodes. VALUE is the resistance (in ohms) and may be positive or negative but not zero.

.NH 2 Capacitors and Inductors

General form:

CXXXXXXX N+ N- VALUE

Examples:

CBYP 13 0 1UF COSC 17 23 10U IC=3V LLINK 42 69 1UH LSHUNT 23 51 10U IC=15.7MA

N+ and N- are the positive and negative element nodes, respectively. VALUE is the capacitance in Farads or the inductance in Henries. For the capacitor, the (optional) initial condition is the initial (time-zero) value of capacitor voltage (in Volts). For the inductor, the (optional) initial condition is the initial (time-zero) value of inductor current (in Amps) that flows from N+, through the inductor, to N-. Note that the initial conditions (if any) apply 'only' if the UIC option is specified on the .TRAN card.

.NH 2 Coupled (Mutual) Inductors

General form:

.NH 2 KXXXXXXX LYYYYYYY LZZZZZZZ VALUE

Examples:

K43 LAA LBB 0.999 KXFRMR L1 L2 0.87

LYYYYYYY and LZZZZZZZ are the names of the two coupled inductors, and VALUE is the coefficient of coupling, K, which must be greater than 0 and less than or equal to 1. Using the 'dot' convention, place a 'dot' on the first node of each inductor.

.NH 2 Transmission Lines (Lossless)

General form:

.NH 2 TXXXXXXX N1 N2 N3 N4 Z0=VALUE

Examples:

T1 1 0 2 0 Z0=50 TD=10NS

N1 and N2 are the nodes at port 1; N3 and N4 are the nodes at port 2. Z0 is the characteristic impedance.

The length of the line may be expressed in either of two forms.

The transmission delay, TD, may be specified directly (as TD=10ns, for example). Alternatively, a frequency F may be given, together with NL, the normalized electrical length of the transmission line with respect to the wavelength in the line at the frequency F.

If a frequency is specified but NL is omitted, 0.25 is assumed (that is, the frequency is assumed to be the quarter-wave frequency). Note that although both forms for expressing the line length are indicated as optional, one of the two must be specified.

Note that this element models only one propagating mode. If all four nodes are distinct in the actual circuit, then two modes may be excited. To simulate such a situation, two transmission- line elements are required. (see the example in Appendix A for further clarification.)

The (optional) initial condition specification consists of the voltage and current at each of the transmission line ports. Note that the initial conditions (if any) apply 'only' if the UIC option is specified on the .TRAN card.

One should be aware that SPICE will use a transient time-step which does not exceed 1/2 the minimum transmission line delay. Therefore very short transmission lines (compared with the analysis time frame) will cause long run times.

.NH 2 Linear Dependent Sources

SPICE allows circuits to contain linear dependent sources characterized by any of the four equations

i=g*v v=e*v i=f*i v=h*i

where g, e, f, and h are constants representing transconductance, voltage gain, current gain, and transresistance, respectively.

Note: a more complete description of dependent sources as implemented in SPICE is given in Appendix B.

.NH 2 Linear Voltage-Controlled Current Sources

General form:

Examples:

G1 2 0 5 0 0.1MMHO

N+ and N- are the positive and negative nodes, respectively. Current flow is from the positive node, through the source, to the negative node. NC+ and NC- are the positive and negative controlling nodes, respectively. VALUE is the transconductance (in mhos).

.NH 2 Linear Voltage-Controlled Voltage Sources

General form:

Examples:

E1 2 3 14 1 2.0

N+ is the positive node, and N- is the negative node. NC+ and NC- are the positive and negative controlling nodes, respec18 tively. VALUE is the voltage gain.

.NH 2 Linear Current-Controlled Current Sources

General form:

Examples:

F1 13 5 VSENS 5

N+ and N- are the positive and negative nodes, respectively. Current flow is from the positive node, through the source, to the negative node. VNAM is the name of a voltage source through which the controlling current flows. The direction of positive controlling current flow is from the positive node, through the source, to the negative node of VNAM. VALUE is the current gain.

.NH 2 Linear Current-Controlled Voltage Sources

General form:

Examples:

HX 5 17 VZ 0.5K

N+ and N- are the positive and negative nodes, respectively. VNAM is the name of a voltage source through which the controlling current flows. The direction of positive controlling current flow is from the positive node, through the source, to the negative node of VNAM. VALUE is the transresistance (in ohms).

.NH 2 Non-Linear Dependent Sources

General form:

Examples:

B1 0 1 I=COS(V(1))+SIN(V(2)) B1 0 1 V=LN(COS(LOG(V(1)-V(2)^2)))-V(3)^4+V(2)^V(1) B1 3 4 I=17 B1 3 4 V=EXP(PI^I(VDD))

N+ is the positive node and N- is the negative node.

The values of the 'V' and 'I' parameters determine the voltages and currents across and through the device, respectively.

If 'I' is given, then the device is a current source, and if 'V' is given then the device is a voltage source.

One, and only one, of these parameters must be given.

The expressions, EXPR, given for 'V' and 'I' may be any function of voltages and currents through voltage sources in the system. The following functions of real variables are defined:

abs asinh cosh sin acos atan exp sinh acosh atanh ln sqrt asin cos log tan

The following operations are defined:

+ - * / unary -

If the values of the circuit variables used in the expressions enter a region where the value of the expression or any of its partial derivatives becomes undefined, an error results.

.NH 2 Independent Sources

General form:

IYYYYYYY N+ N- <

Examples:

VCC 10 0 DC 6 VIN 13 2 0.001 AC 1 SIN(0 1 1MEG) ISRC 23 21 AC 0.333 45.0 SFFM(0 1 10K 5 1K) VMEAS 12 9 VCARRIER 1 0 DISTOF1 0.1 -90.0 VMOD 2 0 DISTOF2 0.01 IIN 1 5 AC 1 DISTOF1 DISTOF2 0.001

N+ and N- are the positive and negative nodes, respectively. Note that voltage sources need not be grounded. Positive current is assumed to flow from the positive node, through the source, to the negative node. A current source of positive value, will force current to flow out of the N+ node, through the source, and into the N- node.

Voltage sources, in addition to being used for circuit excitation, are the 'ammeters' for SPICE, that is, zero valued voltage sources may be inserted into the circuit for the purpose of measuring current. They will, of course, have no effect on circuit operation since they represent short-circuits.

DC/TRAN is the dc and transient analysis value of the source. If the source value is zero both for dc and transient analyses, this value may be omitted.

If the source value is time-invariant (e.g., a power supply), then the value may optionally be preceded by the letters DC.

ACMAG is the ac magnitude and ACPHASE is the ac phase. The source is set to this value in the ac analysis. If ACMAG is omitted following the keyword AC, a value of unity is assumed. If ACPHASE is omitted, a value of zero is assumed.

If the source is not an ac small-signal input, the keyword AC and the ac values are omitted.

DISTOF1 and DISTOF2 are the keywords that specify that the independent source has distortion inputs at the frequencies F1 and F2 respectively. See the description of the DISTO control line.

The keywords may be followed by an optional magnitude and phase. The default values of the magnitude and phase are 1.0 and 0.0 respectively.

Any independent source can be assigned a time-dependent value for transient analysis. If a source is assigned a time-dependent value, the time-zero value is used for dc analysis.

There are five independent source functions:

pulse, exponential, sinusoidal, piece-wise linear, and single-frequency FM.

If parameters other than source values are omitted or set to zero, the default values shown will be assumed.

(TSTEP is the printing increment and TSTOP is the final time (see the .TRAN line for explanation)).

.NH 3 Pulse PULSE(V1 V2 TD TR TF PW PER)

Examples:

VIN 3 0 PULSE(-1 1 2NS 2NS 2NS 50NS 100NS)

V1 (initial value) Volts or Amps V2 (pulsed value) Volts or Amps TD (delay time) 0.0 seconds TR (rise time) TSTEP seconds TF (fall time) TSTEP seconds PW (pulse width) TSTOP seconds PER (period) TSTOP seconds

A single pulse so specified is described by the following table:

0 V1 TD V1 TD+TR V2 TD+TR+PW V2 TD+TR+PW+TF V1 TSTOP V1

Intermediate points are determined by linear interpolation.

.NH 3 Sinusoidal SIN(VO VA FREQ TD THETA)

Examples:

VIN 3 0 SIN(0 1 100MEG 1NS 1E10)

VO (offset) Volts or Amps VA (amplitude) Volts or Amps FREQ (frequency) 1/TSTOP Hz TD (delay) 0.0 seconds THETA (damping factor) 0.0 1/seconds

The shape of the waveform is described by the following table:

0 to TD VO TD to TSTOP VO+VA*exp(-(time-TD)*THETA) *sine(twopi*FREQ*(time+TD))

.NH 3 Exponential EXP(V1 V2 TD1 TAU1 TD2 TAU2)

Examples:

VIN 3 0 EXP(-4 -1 2NS 30NS 60NS 40NS)

V1 (initial value) Volts or Amps V2 (pulsed value) Volts or Amps TD1 (rise delay time) 0.0 seconds TAU1 (rise time constant) TSTEP seconds TD2 (fall delay time) TD1+TSTEP seconds TAU2 (fall time constant) TSTEP seconds

The shape of the waveform is described by the following table:

0 to TD1 V1 TD1 to TD2 V1+(V2-V1)*(1-exp(-(time-TD1)/TAU1)) TD2 to TSTOP V1+(V2-V1)*(1-exp(-(time-TD1)/TAU1)) +(V1-V2)*(1-exp(-(time-TD2)/TAU2))

.NH 3
Piece-Wise Linear PWL(T1 V1

Examples:

VCLOCK 7 5 PWL(0 -7 10NS -7 11NS -3 17NS -3 18NS -7 50NS -7)

Parameters and default values

Each pair of values (Ti, Vi) specifies that the value of the source is Vi (in Volts or Amps) at time=Ti. The value of the source at intermediate values of time is determined by using linear interpolation on the input values.

.NH 3 Single-Frequency FM

Examples:

V1 12 0 SFFM(0 1M 20K 5 1K)

VO (offset) Volts or Amps VA (amplitude) Volts or Amps FC (carrier frequency) 1/TSTOP Hz MDI (modulation index) FS (signal frequency) 1/TSTOP Hz

The shape of the waveform is described by the following equation:

value = VO + VA*sine((twopi*FC*time) + MDI*sine(twopi*FS*time))

.NH 2 Switches

General form:

Examples:

S1 1 2 3 4 SWITCH1 ON S2 5 6 3 0 SM2 OFF SWITCH1 1 2 10 0 SMODEL1 W1 1 2 VCLOCK SWITCHMOD1 W2 3 0 VRAMP SM1 ON WRESET 5 6 VCLCK LOSSYSWITCH OFF

Nodes N+ and N- are the nodes between which the switch terminal are connected. For the voltage-controlled switch, nodes NC+ and NC- are the positive and negative controlling nodes respectively. For the current-controlled switch, the controlling current is that through the VNAME, the specified voltage source.

The direction of positive controlling current flow is from the positive node, through the source, to the negative node.

.NH SEMICONDUCTOR DEVICES

The elements that have been described to this point typically require only a few parameter values to specify completely the electrical characteristics of the element.

However, the models for the four semiconductor devices that are included in the SPICE program require many parameter values. Moreover, many devices in a circuit often are defined by the same set of device model parameters.

For these reasons, a set of device model parameters is defined on a separate .MODEL line and assigned a unique model name. The device element lines in SPICE then reference the model name. This scheme alleviates the need to specify all of the model parameters on each device element card.

Each device element line contains the device name, the nodes to which the device is connected, and the device model name. In addition, other optional parameters may be specified for each device: geometric factors and an initial condition.

The area factor used on the diode, BJT and JFET device line determines the number of equivalent parallel devices of a specified model. The affected parameters are marked with an asterisk under the heading 'area' in the model descriptions below. Several geometric factors associated with the channel and the drain and source diffusions can be specified on the MOSFET device card.

Two different forms of initial conditions may be specified for devices.

The first form is included to improve the dc convergence for circuits that contain more than one stable state. If a device is specified OFF, the dc operating point is determined with the terminal voltages for that device set to zero. After convergence is obtained, the program continues to iterate to obtain the exact value for the terminal voltages.

If a circuit has more than one dc stable state, the OFF option can be used to force the solution to correspond to a desired state. If a device is specified OFF when in reality the device is conducting, the program will still obtain the correct solution (assuming the solutions converge) but more iterations will be required since the program must independently converge to two separate solutions.

The .NODESET line serves a similar purpose as the OFF option. The .NODESET option is easier to apply and is the preferred means to aid convergence.

The second form of initial conditions are specified for use with the transient analysis. These are true 'initial conditions' as opposed to the convergence aids above. See the description of the .IC card and the .TRAN line for a detailed explanation of initial conditions.

.NH 2 Semiconductor Resistors

General form:

Examples:

RLOAD 2 10 10K RMOD 3 7 RMODEL L=10u W=1u

This is the more general form, of the resistor presented in section 6.1, and allows the modelling of temperature effects and for the calculation of the actual resistance value from strictly geometric information, and the specification of the process.

If VALUE is specified, it overrides the geometric information and defines the resistance.

If MNAME is specified, then the resistance may be calculated from the process information in the model MNAME and the given LENGTH and WIDTH.

If VALUE is not specified, then MNAME and LENGTH must be specified.

If WIDTH is not specified, then it is taken from the default width given in the model.

The (optional) TEMP value is the temperature at which this device is to operate, and overrides the temperature specification on the .OPTIONS control line.

.NH 2 Semiconductor Capacitors

General form:

Examples:

CLOAD 2 10 10P CMOD 3 7 CMODEL L=10u W=1u

This is the more general form of the capacitor presented in section 6.2, and allows for the calculation of the actual capacitance value from strictly geometric information, and the specification of the process.

If VALUE is specified, it overrides the geometric information and defines the capacitance.

If MNAME is specified, then the capacitance may be calculated from the process information in the model MNAME and the given LENGTH and WIDTH.

If VALUE is not specified, then MNAME and LENGTH must be specified.

If WIDTH is not specified, then it is taken from the default width given in the model.

Either VALUE or MNAME, LENGTH and WIDTH may be specified, but not both sets.

.NH 2 Uniform Distributed RC Lines

General form:

Examples:

U1 1 2 0 URCMOD L=50U URC2 1 12 2 UMODL L=1mil N=6

N1 and N2 are the two element nodes the RC line connects, while N3 is the node to which the capacitances are connected.

MNAME is the model name, LENGTH is the length of the RC line in metres.

LUMPS, if specified, is the number of lumped segments to use in modelling the RC line. See the model description for the action taken if this parameter is omitted.

.NH 2 Junction Diodes

General form:

Examples:

DBRIDGE 2 10 DIODE1 DCLMP 3 7 DMOD 3.0 IC=0.2

N+ and N- are the positive and negative nodes, respectively. MNAME is the model name, AREA is the area factor, and OFF indicates an (optional) starting condition on the device for dc analysis. If the area factor is omitted, a value of 1.0 is assumed. The (optional) initial condition specification using IC=VD is intended for use with the UIC option on the .TRAN card, when a transient analysis is desired starting from other than the quiescent operating point.

.NH 2 Bipolar Junction Transistors (BJT's)

General form:

Examples:

Q23 10 24 13 QMOD IC=0.6,5.0 Q50A 11 26 4 20 MOD1

NC, NB, and NE are the collector, base, and emitter nodes, respectively. NS is the (optional) substrate node. If unspecified, ground is used. MNAME is the model name, AREA is the area factor, and OFF indicates an (optional) initial condition on the device for the dc analysis. If the area factor is omitted, a value of 1.0 is assumed.

The (optional) initial condition specification using IC=VBE,VCE is intended for use with the UIC option on the .TRAN card, when a transient analysis is desired starting from other than the quiescent operating point. See the .IC line description for a better way to set transient initial conditions.

.NH 2 Junction Field-Effect Transistors (JFET's)

General form:

Examples:

J1 7 2 3 JM1 OFF

ND, NG, and NS are the drain, gate, and source nodes, respectively. MNAME is the model name, AREA is the area factor, and OFF indicates an (optional) initial condition on the device for dc analysis. If the area factor is omitted, a value of 1.0 is assumed.

The (optional) initial condition specification, using IC=VDS,VGS is intended for use with the UIC option on the .TRAN card, when a transient analysis is desired starting from other than the quiescent operating point (see the .IC line for a better way to set initial conditions).

.NH 2 MOSFET's

General form:

Examples:

M1 24 2 0 20 TYPE1 M31 2 17 6 10 MODM L=5U W=2U M31 2 16 6 10 MODM 5U 2U M1 2 9 3 0 MOD1 L=10U W=5U AD=100P AS=100P PD=40U PS=40U M1 2 9 3 0 MOD1 10U 5U 2P 2P

ND, NG, NS, and NB are the drain, gate, source, and bulk (substrate) nodes, respectively.

MNAME is the model name.

L and W are the channel length and width, in meters.

AD and AS are the areas of the drain and source diffusions, in sq-meters.

Note that the suffix U specifies microns (1E-6 m) and P sq-microns (1E-12 sq-m).

If any of L, W, AD, or AS are not specified, default values are used.

The user may specify the values to be used for these default parameters on the .OPTIONS card. The use of defaults simplifies input file preparation, as well as the editing required if device geometries are to be changed.

PD and PS are the perimeters of the drain and source junctions, in meters.

NRD and NRS designate the equivalent number of squares of the drain and source diffusions; these values multiply the sheet resistance RSH specified on the .MODEL line for an accurate representation of the parasitic series drain and source resistance of each transistor.

PD and PS default to 0.0 while NRD and NRS to 1.0.

OFF indicates an (optional) initial condition on the device for dc analysis. The (optional) initial condition specification using IC=VDS,VGS,VBS is intended for use with the UIC option on the .TRAN card, when a transient analysis is desired starting from other than the quiescent operating point. See the .IC line for a better and more convenient way to specify transient initial conditions. .NH 2 .MODEL Line

General form:

Examples:

.MODEL MOD1 NPN BF=50 IS=1E-13 VBF=50

The .MODEL line specifies a set of model parameters that will be used by one or more devices. MNAME is the model name, and type is one of the following fourteen types:

R silicon resistor C silicon capacitor URC Uniform Distributed RC line D diode model NPN NPN BJT model PNP PNP BJT model NJF N-channel JFET model PJF P-channel JFET model NMOS N-channel MOSFET model PMOS P-channel MOSFET model NMF N-channel MOSFET model PMF P-channel MOSFET model SW voltage-controlled switch CSW current-controlled switch

Parameter values are defined by appending the parameter name, as given below for each model type, followed by an equal sign and the parameter value. Model parameters that are not given a value are assigned the default values given below for each model type.

.NH 2 Resistor Model

The resistor model consists of process-related device data that allow the resistance to be calculated from geometric information and to be corrected for temperature. The parameters available are:

TC1 1st order temp coeff ohm/degC 0.0 TC2 2nd order temp coeff ohm/degC 0.0 RSH sheet resistance ohm/sq - 50 DEFW default width metres 1e-6 2e-6 NARROW narrowing due to side etching metres 0.0 1e-7 TNOM parameter measurement temp degC 27 50

The sheet resistance is used with the narrowing parameter and L and W from the resistor device to determine the nominal resistance by the formula:

R = RSH * (L-NARROW) / (W-NARROW)

DEFW is used to supply a default value for W if one is not specified for the device. If either RSH or L is not specified, then the standard default resistance value of 1K is used. TNOM is used to override the circuit-wide value given on the .OPTIONS control line where the parameters of this model have been measured at a different temperature. After the nominal resistance is calculated, it is adjusted for temperature by the formula:

R(t) = R(t0)[1+TC1(t-t0) + TC2(t-t0)**2]

.NH 2 Capacitor Model

The capacitor model contains process information that may be used to compute the capacitance from strictly geometric information.

CJ junction bottom cap F/m**2 - 5e-5 CJSW junction sidewall cap F/m**2 - 2e-11 DEFW default width metres 1e-6 2e-6 NARROW narrowing due to side etching metres 0.0 1e-7

The capacitor has a capacitance computed as:

CAP = CJ(LENGTH-NARROW)(WIDTH-NARROW) + 2.CJSW(LENGTH + WIDTH - 2.NARROW)

.NH 2 Uniform Distributed RC Model

The URC model is derived from a model proposed by L.Gertzberg in 1974. The model is accomplished by a subcircuit-type expansion of the URC line into a network of lumped RC segments with internally-generated nodes. The RC segments are in a geometric progression, increasing toward the middle of the URC line, with K as a proportionality constant. The number of lumped segments used, if not specified for the URC line device, is determined by the following formula:

N = log[Fmax(R/L)(C/L)(TWOPI.L**2)((K-I)/K)**2] / logK

The URC line is made up strictly of resistor and capacitor segments unless the ISPERL parameter is given a non-zero value, in which case the capacitors are replaced with reverse-biased diodes with a zero-bias junction capacitance equivalent to the capacitance replaced, and with a saturation current of ISPERL amps per metre of transmission line and an optional series resistance equivalent to RSPERL ohms per metre.

K Propagation constant 2.0 1.25 FMAX Max freq of interest Hz 1.0G 6.5Meg RPERL Res per unit length ohm/m 1000 10 CPERL cap per unit length F/m 1.0e-15 1pF ISPERL sat current per unit length A/m 0 - RSPERL Diode res per unit length ohm/m 0 -

.NH 2 Switch Model

The switch model allows an almost ideal switch to be described in SPICE. The switch is not quite ideal in that the resistance cannot change from 0 to infinity, but must always have a finite positive value. By proper selection of the on and off resistances, they can be effectively zero and infinity in comparison to other circuit elements. The parameters available are:

VT threshold voltage volts 0.0 S IT threshold current amps 0.0 W VH hysteresis voltage volts 0.0 S VH hysteresis current amps 0.0 W RON on resistance ohms 1.0 both ROFF off resistance ohms 1/GMIN both

See the .OPTIONS control line for a description of GMIN, whose default value results in an off resistance of 1E+12 ohms.

The use of an ideal element that is highly non-linear such as a switch can cause large discontinuities to occur in the circuit node voltages. A rapid change such as that associated with a switch changing state can cause numerical roundoff or tolerance problems leading to erroneous results or timestep difficulties. The user of switches can improve the situation by taking the following steps:

First of all it is wise to set ideal switch impedances only high and low enough to be negligible with respect to other circuit elements. Using switch impedances that are close to "ideal" in all cases aggravates the problem of discontinuities mentioned above. Of course, when modelling real devices such as MOSFETS, the on-resistance should be adjusted to a realistic level depending on the size of the device being modelled.

If a wide range of ON to OFF resistances must be used in the switches, (ROFF/RON > 1E12) then the tolerance on errors allowed during transient analysis should be increased using the .OPTIONS control line and specifying TRTOL to be less than the default value of 7.0. When switches are placed around capacitors, then the option CHGTOL should also be reduced. Suggested values for these two options are 1.0 and 1E-16 respectively. These changes inform SPICE3 to be more careful around the switch points so that no errors are made due to the rapid change in the circuit.

.NH 2 Diode Model

The dc characteristics of the diode are determined by the parameters IS and N. An ohmic resistance, RS, is included. Charge storage effects are modeled by a transit time, TT, and a nonlinear depletion layer capacitance which is determined by the parameters CJO, VJ, and M. The temperature dependence of the saturation current is defined by the parameters EG, the energy and XTI, the saturation current temperature exponent. Reverse breakdown is modeled by an exponential increase in the reverse diode current and is determined by the parameters BV and IBV (both of which are positive numbers).

1 IS saturation current A 1.0E-14 1.0E-14 2 RS ohmic resistance Ohm 0 10 3 N emission coefficient 1 1.0 4 TT transit-time sec 0 0.1Ns 5 CJO zero-bias junction cap F 0 2PF 6 VJ junction potential V 1 0.6 7 M grading coefficient 0.5 0.5 8 EG activation energy eV 1.11 1.11 Si 0.69 Sbd 0.67 Ge 9 XTI saturation-current temp. exp 3.0 3.0 jn 2.0 Sbd 10 KF flicker noise coefficient 0 11 AF flicker noise exponent 1 12 FC coefficient for forward-bias 0.5 depletion capacitance formula 13 BV reverse breakdown voltage V infinite 40.0 14 IBV current at breakdown voltage A 1.0E-3

.NH 2 BJT Models (both NPN and PNP)

The bipolar junction transistor model in SPICE is an adaptation of the integral charge control model of Gummel and Poon. This modified Gummel-Poon model extends the original model to include several effects at high bias levels.

The model will automatically simplify to the simpler Ebers-Moll model when certain parameters are not specified.

The parameter names used in the modified Gummel-Poon model have been chosen to be more easily understood by the program user, and to reflect better both physical and circuit design thinking.

The dc model is defined by the parameters IS, BF, NF, ISE, IKF, and NE which determine the forward current gain characteristics, IS, BR, NR, ISC, IKR, and NC which determine the reverse current gain characteristics, and VAF and VAR which determine the output conductance for forward and reverse regions.

Three ohmic resistances RB, RC, and RE are included, where RB can be high current dependent.

Base charge storage is modeled by forward and reverse transit times, TF and TR, the forward transit time TF being bias dependent if desired, and nonlinear depletion layer capacitances which are determined by CJE, VJE, and MJE for the B-E junction , CJC, VJC, and MJC for the B-C junction and CJS, VJS, and MJS for the C-S (Collector-Substrate) junction.

The temperature dependence of the saturation current, IS, is determined by the energy-gap, EG, and the saturation current temperature exponent, XTI. Additionally base current temperature dependence is modeled by the beta temperature exponent XTB in the new model.

The BJT parameters used in the modified Gummel-Poon model are listed below. The parameter names used in earlier versions of SPICE2 are still accepted.

IS transport saturation current A 1.0E-16 1.0E-15 BF ideal maximum forward beta 100 100 NF forward current emission coefficient 1.0 1 VAF forward Early voltage V infinite 200 IKF corner for forward beta high current roll-off A infinite 0.01 ISE B-E leakage saturation current A 0 1.0E-13 NE B-E leakage emission coefficient 1.5 2 BR ideal maximum reverse beta 1 0.1 NR reverse current emission coefficient 1 1 VAR reverse Early voltage V infinite 200 IKR corner for reverse beta high current roll-off A infinite 0.01 ISC B-C leakage saturation current A 0 1.0E-13 NC B-C leakage emission coefficient 2 1.5 RB zero bias base resistance Ohms 0 100 IRB current where base resistance falls halfway to its min value A infinite 0.1 RBM minimum base resistance at high currents Ohms RB 10 RE emitter resistance Ohms 0 1 RC collector resistance Ohms 0 10 CJE B-E zero-bias depletion capacitance F 0 2PF VJE B-E built-in potential V 0.75 0.6 MJE B-E junction exponential factor 0.33 0.33 TF ideal forward transit time sec 0 0.1Ns XTF coefficient for bias dependence of TF 0 VTF voltage describing VBC dependence of TF V infinite ITF high-current parameter for effect on TF A 0 PTF excess phase at freq=1.0/(TF*2PI) Hz deg 0 CJC B-C zero-bias depletion capacitance F 0 2PF * VJC B-C built-in potential V 0.75 0.5 MJC B-C junction exponential factor 0.33 0.5 XCJC fraction of B-C depletion capacitance 1 connected to internal base node TR ideal reverse transit time sec 0 10Ns CJS zero-bias collector-substrate capacitance F 0 2PF * VJS substrate junction built-in potential V 0.75 MJS substrate junction exponential factor 0 0.5 XTB forward and reverse beta temperature exponent 0 EG energy gap for temperature effect on IS eV 1.11 XTI temperature exponent for effect on IS 3 KF flicker-noise coefficient 0 AF flicker-noise exponent 1 FC coefficient for forward-bias depletion capacitance formula 0.5

.NH 2 JFET Models (both N and P Channel)

The JFET model is derived from the FET model of Shichman and Hodges. The dc characteristics are defined by the parameters VTO and BETA, which determine the variation of drain current with gate voltage, LAMBDA, which determines the output conductance, and IS, the saturation current of the two gate junctions.

Two ohmic resistances, RD and RS, are included. Charge storage is modeled by nonlinear depletion layer capacitances for both gate junctions which vary as the -1/2 power of junction voltage and are defined by the parameters CGS, CGD, and PB.

VTO threshold voltage V -2.0 -2.0 BETA transconductance parameter A/V**2 1.0E-4 1.0E-3 LAMBDA channel length modulation parameter 1/V 0 1.0E-4 RD drain ohmic resistance Ohm 0 100 RS source ohmic resistance Ohm 0 100 CGS zero-bias G-S junction capacitance F 0 5PF CGD zero-bias G-D junction capacitance F 0 1PF PB gate junction potential V 1 0.6 IS gate junction saturation current A 1.0E-14 1.0E-14 KF flicker noise coefficient 0 AF flicker noise exponent 1 FC coefficient for forward-bias 0.5 depletion capacitance formula

.NH 2 MOSFET Models (both N and P channel)

SPICE provides three MOSFET device models which differ in the formulation of the I-V characteristic. The variable LEVEL specifies the model to be used:

LEVEL=1 -> Shichman-Hodges LEVEL=2 -> MOS2 (as described in [1]) LEVEL=3 -> MOS3, a semi-empirical model(see [1])

The dc characteristics of the MOSFET are defined by the device parameters VTO, KP, LAMBDA, PHI and GAMMA. These parameters are computed by SPICE if process parameters (NSUB, TOX, ...) are given, but user-specified values always override.

VTO is positive (negative) for enhancement mode and negative (positive) for depletion mode N-channel (P-channel) devices.

Charge storage is modeled by three constant capacitors, CGSO, CGDO, and CGBO which represent overlap capacitances, by the nonlinear thin-oxide capacitance which is distributed among the gate, source, drain, and bulk regions, and by the nonlinear depletion-layer capacitances for both substrate junctions divided into bottom and periphery, which vary as the MJ and MJSW power of junction voltage respectively, and are determined by the parameters CBD, CBS, CJ, CJSW, MJ, MJSW and PB.

There are two built-in models of the charge storage effects associated with the thin-oxide. The default is the piecewise linear voltage-dependent capacitance model proposed by Meyer. The second choice is the charge-controlled capacitance model of Ward and Dutton [1].

The XQC model parameter acts as a flag and a coefficient at the same time. As the former it causes the program to use Meyer's model whenever larger than 0.5 or not specified, and the charge-controlled model when between 0 and 0.5. In the latter case its value defines the share of the channel charge associated with the drain terminal in the saturation region.

The thin-oxide charge storage effects are treated slightly different for the LEVEL=1 model. These voltage dependent capacitances are included only if TOX is specified in the input description and they are represented using Meyer's formulation.

There is some overlap among the parameters describing the junctions, e.g. the reverse current can be input either as IS (in A) or as JS (in A/m**2). Whereas the first is an absolute value the second is multiplied by AD and AS to give the reverse current of the drain and source junctions respectively. This methodology has been chosen since there is no sense in relating always junction characteristics with AD and AS entered on the device card; the areas can be defaulted.

The same idea applies also to the zero-bias junction capacitances CBD and CBS (in F) on one hand, and CJ (in F/m**2) on the other.

The parasitic drain and source series resistance can be expressed as either RD and RS (in ohms) or RSH (in ohms/sq.), the latter being multiplied by the number of squares NRD and NRS input on the device card.

LEVEL model index 1 VTO zero-bias threshold voltage V 0.0 1.0 KP transconductance parameter A/V**2 2.0E-5 3.1E-5 GAMMA bulk threshold parameter V**0.5 0.0 0.37 PHI surface potential V 0.6 0.65 LAMBDA channel-length modulation (MOS1 and MOS2 only) 1/V 0.0 0.02 RD drain ohmic resistance Ohm 0.0 1.0 RS source ohmic resistance Ohm 0.0 1.0 CBD zero-bias B-D junction capacitance F 0.0 20FF CBS zero-bias B-S junction capacitance F 0.0 20FF IS bulk junction saturation current A 1.0E-14 1.0E-15 PB bulk junction potential V 0.8 0.87 CGSO gate-source overlap capacitance per meter channel width F/m 0.0 4.0E-11 CGDO gate-drain overlap capacitance per meter channel width F/m 0.0 4.0E-11 CGBO gate-bulk overlap capacitance per meter channel length F/m 0.0 2.0E-10 RSH drain and source diffusion sheet resisitance Ohm/sq. 0.0 10.0 CJ zero-bias bulk junction bottom cap. per sq-meter of junction area F/m**2 0.0 2.0E-4 MJ bulk junction bottom grading coef. 0.5 0.5 CJSW zero-bias bulk junction sidewall cap. per meter of junction perimeter F/m 0.0 1.0E-9 MJSW bulk junction sidewall grading coef. 0.33 JS bulk junction saturation current per sq-meter of junction area A/m**2 1.0E-8 TOX oxide thickness meter 1.0E-7 1.0E-7 NSUB substrate doping 1/cm**3 0.0 4.0E15 NSS surface state density 1/cm**2 0.0 1.0E10 NFS fast surface state density 1/cm**2 0.0 1.0E10 TPG type of gate material: 1.0 +1 opp. to substrate -1 same as substrate 0 Al gate XJ metallurgical junction depth meter 0.0 1U LD lateral diffusion meter 0.0 0.8U UO surface mobility cm**2/V-s 600 700 UCRIT critical field for mobility degradation (MOS2 only) V/cm 1.0E4 1.0E4 UEXP critical field exponent in mobility degradation (MOS2 only) 0.0 0.1 UTRA transverse field coef (mobility) (deleted for MOS2) 0.0 0.3 VMAX maximum drift velocity of carriers m/s 0.0 5.0E4 NEFF total channel charge (fixed and mobile) coefficient (MOS2 only) 1.0 5.0 XQC thin-oxide capacitance model flag and coefficient of channel charge share attributed to drain (0-0.5) 1.0 0.4 KF flicker noise coefficient 0.0 1.0E-26 AF flicker noise exponent 1.0 1.2 FC coefficient for forward-bias depletion capacitance formula 0.5 DELTA width effect on threshold voltage (MOS2 and MOS3) 0.0 1.0 THETA mobility modulation (MOS3 only) 1/V 0.0 0.1 ETA static feedback (MOS3 only) 0.0 1.0 KAPPA saturation field factor (MOS3 only) 0.2 0.5

.NH 2 MESFET Models (both N and P channel)

The MESFET model is derived from the GaAs FET model of Statz et al. as described in [6]. The d.c characteristics are defined by the parameters VTO, B and BETA, which determine the variation of drain current with gate voltage, ALPHA, which determines saturation voltage, and LAMBDA, which determines the output conductance.

Two ohmic resistances, RD and RS, are included. Charge storage is modelled by total gate charge as a function of gate-drain and gate-source voltages and is defined by the parameters CGS, CGD and PB.

VTO pinch-off voltage V -2.0 -2.0 BETA transconductance parameter A/V**2 1e-4 1e-3 B doping tail extending parameter 1/V 0.3 0.3 ALPHA saturation voltage parameter 1/V 2 2 LAMBDA channel length modulation parameter 1/V 0 1e-4 RD drain ohmic resistance ohms 0 100 RS source ohmic resistance ohms 0 100 CGS zero-bias G-S junction C F 0 5pF CGD zero-bias G-D junction C F 0 1pF PB gate junction potential V 1 0.6 KF flicker noise coefficient 0 AF flicker noise exponent 1 FC coefficient for forward-bias 0.5 depletion capacitance formula

[1] A. Vladimirescu and S. Liu, "The Simulation of MOS Integrated Circuits Using SPICE2", ERL Memo No. ERL M80/7,Electronics Research Laboratory, University of California, Berkeley, Oct. 1980.

.NH SUBCIRCUITS

A subcircuit that consists of SPICE elements can be defined and referenced in a fashion similar to device models.

The subcircuit is defined in the input file by a grouping of element cards; the program then automatically inserts the group of elements wherever the subcircuit is referenced.

There is no limit on the size or complexity of subcircuits, and subcircuits may contain other subcircuits. An example of subcircuit usage is given in Appendix A.

.NH 2 .SUBCKT Line

General form:

Examples:

.SUBCKT OPAMP 1 2 3 4 39

A circuit definition is begun with a .SUBCKT card. SUBNAM is the subcircuit name, and N1, N2, ... are the external nodes, which cannot be zero. The group of element lines which immediately follow the .SUBCKT line define the subcircuit. The last line in a subcircuit definition is the .ENDS line (see below).

Control lines may not appear within a subcircuit definition; however, subcircuit definitions may contain anything else, including other subcircuit definitions, device models, and subcircuit calls (see below).

Note that any device models or subcircuit definitions included as part of a subcircuit definition are strictly local (i.e., such models and definitions are not known outside the subcircuit definition).

Also, any element nodes not included on the .SUBCKT line are strictly local, with the exception of 0 (ground) which is always global.

.NH 2 .ENDS Line

General form:

Examples:

.ENDS OPAMP

This line must be the last one for any subcircuit definition. The subcircuit name, if included, indicates which subcircuit definition is being terminated; if omitted, all subcircuits 40 being defined are terminated. The name is needed only when nested subcircuit definitions are being made.

.NH 2 Subcircuit Calls

General form:

Examples:

X1 2 4 17 3 1 MULTI

Subcircuits are used in SPICE by specifying pseudo-elements beginning with the letter X, followed by the circuit nodes to be used in expanding the subcircuit.

.NH CONTROL LINES

.NH 2 .OPTIONS Line

General form:

Examples:

.OPTIONS ACCT LIST NODE

This line allows the user to reset program control and user options for specific simulation purposes. Any combination of the following options may be included, in any order. 'x' (below) represents some positive number.

GMIN=x resets the value of GMIN, the minimum conductance allowed by the program. The default value is 1.0E-12. RELTOL=x resets the relative error tolerance of the program. The default value is 0.001 (0.1 percent). ABSTOL=x resets the absolute current error tolerance of the program. The default value is 1 picoamp. VNTOL=x resets the absolute voltage error tolerance of the program. The default value is 1 microvolt. TRTOL=x resets the transient error tolerance. The default value is 7.0 This parameter is an estimate of the factor by which SPICE overestimates the actual truncation error. CHGTOL=x resets the charge tolerance of the program. The default value is 1.0E-14. PIVTOL=x resets the absolute minimum value for a matrix entry to be accepted as a pivot. The default value is 1.0E-13. PIVREL=x resets the relative ratio between the largest column entry and an acceptable pivot value. The default value is 1.0E-3. In the numerical pivoting algorithm the allowed minimum pivot value is determined by EPSREL=AMAX1(PIVREL*MAXVAL,PIVTOL) where MAXVAL is the maximum element in the column where a pivot is sought (partial pivoting). TNOM=x resets the nominal temperature. The default value is 27 deg C (300 deg K). TNOM can be overridden by a specification on on any temperature-dependent device model. ITL1=x resets the dc iteration limit. The default is 100. ITL2=x resets the dc transfer curve iteration limit. The default is 50. ITL5=x resets the transient analysis total iteration limit. the default is 5000. Set ITL5=0 to omit this test. DEFL=x resets the value for MOS channel length; the default is 100.0 micrometer. DEFW=x resets the value for MOS channel width; the default is 100.0 micrometer. DEFAD=x resets the value for MOS drain diffusion area; the default is 0.0. DEFAS=x resets the value for MOS source diffusion area; the default is 0.0.

.NH 2 .DC Line

General form:

Examples:

.DC VIN 0.25 5.0 0.25 .DC VDS 0 10 .5 VGS 0 5 1 .DC VCE 0 10 .25 IB 0 10U 1U

This line defines the dc transfer curve source and sweep limits.

SRCNAM is the name of an independent voltage or current source. VSTART, VSTOP, and VINCR are the starting, final, and incrementing values respectively.

The first example will cause the value of the voltage source VIN to be swept from 0.25 Volts to 5.0 Volts in increments of 0.25 Volts.

A second source (SRC2) may optionally be specified with associated sweep parameters. In this case, the first source will be swept over its range for each value of the second source.

This option can be useful for obtaining semiconductor device output characteristics. See the second example data file in that section of the guide.

.NH 2 .NODESET Line

General form:

Examples:

.NODESET V(12)=4.5 V(4)=2.23

This line helps the program find the dc or initial transient solution by making a preliminary pass with the specified nodes held to the given voltages.

The restriction is then released and the iteration continues to the true solution. The .NODESET line may be necessary for convergence on bistable or astable circuits. In general, this line should not be necessary.

.NH 2 .IC Line

General form:

Examples:

.IC V(11)=5 V(4)=-5 V(2)=2.2

This line is for setting transient initial conditions.

It has two different interpretations, depending on whether the UIC parameter is specified on the .TRAN control line. Also, one should not confuse this line with the .NODESET line.

The .NODESET line is only to help dc convergence, and does not affect final bias solution (except for multi-stable circuits).

The two interpretations of this line are as follows:

1. When the UIC parameter is specified on the .TRAN line, then the node voltages specified on the .IC line are used to compute the capacitor, diode, BJT, JFET, and MOSFET initial conditions.

This is equivalent to specifying the IC=... parameter on each device line, but is much more convenient. The IC=... parameter can still be specified and will take precedence over the .IC values.

Since no dc bias (initial transient) solution is computed before the transient analysis, one should take care to specify all dc source voltages on the .IC line if they are to be used to compute device initial conditions.

2. When the UIC parameter is not specified on the .TRAN line, the dc bias (initial transient) solution will be computed before the transient analysis. In this case, the node voltages specified on the .IC line will be forced to the desired initial values during the bias solution.

During transient analysis, the constraint on these node voltages is removed. This is the preferred method, since it allows SPICE to compute a consistent dc solution.

.NH 2 .TF Line

General form:

Examples:

.TF V(5,3) VIN

.TF I(VLOAD) VIN

This line defines the small-signal output and input for the dc small-signal analysis. OUTVAR is the small-signal output variable and INSRC is the small-signal input source.

If this line is included, SPICE will compute the dc small-signal value of the transfer function (output/input), input resistance, and output resistance.

For the first example, SPICE would compute the ratio of V(5,3) to VIN, the small-signal input resistance at VIN, and the small-signal output resistance measured across nodes 5 and 3.

.NH 2 .SENS Line

General form:

Examples:

.SENS V(9) V(4,3) V(17) I(VCC)

If a .SENS line is included in the input file, SPICE will determine the dc small-signal sensitivities of each specified output variable with respect to every circuit parameter. Note: for large circuits, large amounts of output can be generated.

.NH 2 .AC Line

General form:

Examples:

.AC DEC 10 1 10K .AC DEC 10 1K 100MEG .AC LIN 100 1 100HZ

DEC stands for decade variation, and ND is the number of points per decade.

OCT stands for octave variation, and NO is the number of points per octave.

LIN stands for linear variation, and NP is the number of points.

FSTART is the starting frequency, and FSTOP is the final frequency.

If this line is included in the file, SPICE will perform an ac analysis of the circuit over the specified frequency range. Note that in order for this analysis to be meaningful, at least one independent source must have been specified with an ac value.

.NH 2 .DISTO Line

General form:

Examples:

.DISTO DEC 10 1kHz 100MHz .DISTO DEC 10 1kHz 100MHz 0.9

This line does a small-signal distortion analysis of the circuit.

A multi-dimensional Volterra series analysis is done using multi-dimensional Taylor series to represent the non-linearities at the operating point. Terms of up to third order are used in the series expansion.

If the optional parameter F2OVERF1 is not specified, .DISTO does a harmonic analysis - i.e, it analyses distortion in the circuit using only a single input frequency F1, which is swept as specified by arguments of the .DISTO command, exactly as in the .AC command.

Inputs at this frequency may be present at more than one input source, and their magnitudes and phases are specified by the arguments of the DISTOF1 keyword in the input file lines for the input sources (see the description of independent sources). The arguments of the DISTOF2 keyword are not relevant in this case.

The analysis produces information about about the AC values of all node voltages and branch currents at the harmonic frequencies 2F1 and 3F1, vs the input frequency F1 as it is swept.

A value of unity (as a complex distortion output) signifies: cos(2PI(2F1).t) at 2F1 and cos(2PI(3F1).t) at 3F1,

using the convention that unity at the fundamental frequency is equivalent to cos(2PI(F1).t).

The distortion component desired - 2F1 or 3F1 - can be selected using commands in Nutmeg, and then printed or plotted. Normally, one is interested primarily in the magnitude of the harmonic components, so the magnitude of the AC distortion value is looked at.

It should be noted that these are the AC values of the actual harmonic components, and are NOT equal to HD2 and HD3. To obtain HD2 and HD3, one must divide bt the corresponding values at F1, obtained from a .AC line.

This division can be done using nutmeg commands.

If the optiional F2OVERF1 parameter is specified, it should be a real number between (and not equal to) zero and unity. In this case, .DISTO does a spectral analysis.

It considers the circuit with sinusoidal inputs, at two different frequencies, F1 and F2. F1 is swept according to the .DISTO control line options, exactly as in the .AC control line. F2 is kept fixed at a single frequency as F1 sweeps: the value at which it is kept fixed is F2OVERF1 times FSTART.

Each independent source in the circuit may potentially have two (superimposed) sinusoidal inputs for distortion, at the frequencies F1 and F2. The magnitude and phase of the F1 component are specified by the arguments of the DISTOF1 keyword in the source's input line (see the description of independent sources). The magnitude and phase of the F2 component are specified in the arguments of the DISTOF2 keyword.

The analysis produces plots of all node voltages/branch currents in the intermodulation product frequencies F1+F2, F1-F2 and 2F1-F2, vs the swept frequency F1. The I.M product of interest may be selected using the SETPLOT command and displayed with the print and plot commands.

It is to be noted that, as in the harmonic analysis case, the results are the actual AC voltages and currents at the intermodulation frequencies, and need to be normalised with respect to the .AC values to obtain the IM parameters.

If the DISTOF1 or DISTOF2 keywords are missing from the description of an independent source, then that source is assumed to have no input at the corresponding frequency. The default values of the magnitude and phase are unity and zero respectively. The phase should be specified in degrees.

It should be carefully noted that F2OVERF1 shoould ideally be an irrational number and that, since this is not possible in practice, efforts should be made to keep the denominator in its representation as large as possible - certainly above 3 - for accurate results.

In other words, if F2OVERF1 is represented as a fraction A/B, where A and B are integers with no common factors, B should be as large as possible. Note that A < B because F2OVERF1 is constrained to be < 1.

To illustrate why, consider the cases where F2OVERF1 is 49/100 and 1/2.

In a spectral analysis, the outputs produced are F1+F2, F1-F2 and 2F1-F2. In the latter case, F1-F2 = F2, so the result at the F1-F2 component is erroneous, because there is the strong F2 component at the same frequency.

Also, F1+F2 = 2F1-F2 in the latter case, and each result is erroneous individually. The problem is not there in the case F2OVERF1 = 49/100, because F1-F2 = 51/100.F1 != 49/100.F1 = F2. In this case, there are two very closely spaced frequency components at F2 and F1-F2.

One of the advantages of the Volterra series technique, is that it computes distortions at mix frequencies expressed symbolically (i.e n.F1 +/- m.F2), therefore, one is able to obtain the strengths of distortion components accurately, even if the separation between them is very small, as opposed to transient analysis, for example.

The disadvantage is, of course, that if two of the mix frequencies coincide, the results are not merged together and presented (though this could, presumably, be done as a post-processing step. Currently, the interested user should keep track of the mix frequencies personally, and add the distortions at coinciding mix frequencies together, should it be necessary.

.NH 2 .NOISE Line

General form:

Examples:

.NOISE V(5) VIN DEC 10 1kHz 100MHz .NOISE V(5) V1 OCT 8 1.0 1.0E6 1

This line does a noise analysis of the circuit.

OUTV is the node at which the total output noise is desired.

INSRC is the name of the independent voltage or current source to which noise is referred.

PTS FSTART FSTOP are .AC type parameters that specify the frequency range over which plots are desired.

PTS_PER_SUMMARY is an optional integer. If specified, the noise contributions of each noise generator is produced every PTS_PER_SUMMARY frequency points.

The .NOISE control line produces two plots - one for the Noise Spectral Density curves, and one for the Total Integrated Noise over the specified frequency range. All noise voltages/currents are in squared units, (V**2/Hz and A**2/Hz for spectral density, and V**2 and A**2 for integrated noise).

.NH 2 .TRAN Line

General form:

Examples:

.TRAN 1NS 100NS .TRAN 1NS 1000NS 500NS .TRAN 10NS 1US UIC

TSTEP is the printing or plotting increment for line-printer output. For use with the post-processor, TSTEP is the suggested computing increment.

TSTOP is the final time, and TSTART is the initial time. If TSTART is omitted, it is assumed to be zero.

The transient analysis always begins at time zero.

In the interval

TMAX is the maximum stepsize that SPICE will use (for default, the program chooses either TSTEP or (TSTOP-TSTART)/50.0, whichever is smaller.

TMAX is useful when one wishes to guarantee a computing interval which is smaller than the printer increment, TSTEP.

UIC (use initial conditions) is an optional keyword which indicates that the user does not want SPICE to solve for the quiescent operating point before beginning the transient analysis.

If this keyword is specified, SPICE uses the values specified using IC=... on the various elements as the initial transient condition and proceeds with the analysis.

If the .IC line has been specified, then the node voltages on the .IC card are used to compute the intitial conditions for the devices. Look at the description on the .IC line for its interpretation when UIC is not specified.

.NH 2 .PZ Line

General Form:

Examples:

.PZ 1 0 3 0 CUR POL .PZ 2 3 5 0 VOL ZER .PZ 4 1 4 1 CUR PZ

CUR stands for a tranfer function of the type (output voltage)/(input current) while VOL stands for a transfer function of the type (output voltage)/(input voltage).

POL stands for pole analysis only, ZER for zero analysis only, and PZ for both.

This feature is provided mainly because if there is a non-convergence in finding poles or zeros, then at least the other may be found.

Finally, NODE1, and NODE2 are the two input nodes, and NODE3 and NODE4 are the two output nodes. Thus, there is complete freedom regarding the output and input ports and the type of transfer function. To print the results, one should use the command PRINT PZ ALL.

.NH 2 .FOUR Line

General form:

Examples:

.FOUR 100K V(5)

This line controls whether SPICE performs a Fourier analysis as a part of the transient analysis.

FREQ is the fundamental frequency, and OV1, ..., are the output variables for which the analysis is desired.

The Fourier analysis is performed over the interval

For maximum accuracy, TMAX (see the .TRAN card) should be set to period/100.0 (or less for very high-Q circuits).

.NH 2 .PRINT Lines

General form:

Examples:

.PRINT TRAN V(4) I(VIN) .PRINT AC VM(4,2) VR(7) VP(8,3) .PRINT DC V(2) I(VSRC) V(23,17) .PRINT NOISE INOISE .PRINT DISTO HD3 SIM2(DB)

This line defines the contents of a tabular listing of one to eight output variables.

PRTYPE is the type of the analysis (DC, AC, TRAN, NOISE, or DISTO) for which the specified outputs are desired.

The form for voltage or current output variables is as follows:

V(N1<,N2>)

specifies the voltage difference between nodes N1 and N2. If N2 (and the preceding comma) is omitted, ground (0) is assumed.

For the ac analysis, five additional outputs can be accessed by replacing the letter V by:

VR - real part VI - imaginary part VM - magnitude VP - phase VDB - 20*log10(magnitude)

I(VXXXXXXX) specifies the current flowing in the independent voltage source named VXXXXXXX.

Positive current flows from the positive node, through the source, to the negative node. For the ac analysis, the corresponding replacements for the letter I may be made in the same way as described for voltage outputs.

Output variables for the noise and distortion analyses have a different general form from that of the other analyses, i.e.

OV<(X)>

where OV is any of ONOISE (output noise), INOISE (equivalent input noise), D2, HD3, SIM2, DIM2, or DIM3 (see description of distortion analysis), and X may be any of:

R - real part I - imaginary part M - magnitude (default if nothing specified) P - phase DB - 20*log10(magnitude)

thus, SIM2 (or SIM2(M)) describes the magnitude of the SIM2 dis- tortion measure, while HD2(R) describes the real part of the HD2 distortion measure. There is no limit on the number of .PRINT cards for each type of analysis.

.NH 2 .PLOT Lines

General form:

Examples:

.PLOT DC V(4) V(5) V(1) .PLOT TRAN V(17,5) (2,5) I(VIN) V(17) (1,9) .PLOT AC VM(5) VM(31,24) VDB(5) VP(5) .PLOT DISTO HD2 HD3(R) SIM2 .PLOT TRAN V(5,3) V(4) (0,5) V(7) (0,10)

This line defines the contents of one plot of from one to eight output variables.

PLTYPE is the type of analysis (DC, AC, TRAN, NOISE, or DISTO) for which the specified outputs are desired.

The syntax for the OVI is identical to that for the .PRINT card, described above.

The optional plot limits (PLO,PHI) may be specified after any of the output variables. All output variables to the left of a pair of plot limits (PLO,PHI) will be plotted using the same lower and upper plot bounds. If plot limits are not specified, SPICE will automatically determine the minimum and maximum values of all output variables being plotted and scale the plot to fit. More than one scale will be used if the output variable values warrant (i.e., mixing output variables with values which are orders-of-magnitude different still gives readable plots). The overlap of two or more traces on any plot is indicated by the letter X. When more than one output variable appears on the same plot, the first variable specified will be printed as well as plotted. If a printout of all variables is desired, then a companion .PRINT line should be included. There is no limit on the number of .PLOT lines specified for each type of analysis.

.NH APPENDIX A: EXAMPLE DATA DECKS

.NH 2 Circuit 1

The following file determines the dc operating point and small-signal transfer function of a simple differential pair. In addition, the ac small-signal response is computed over the frequency range 1Hz to 100MEGHz.

.NH 2 Circuit 2

The following file computes the output characteristics of a MOSFET device over the range 0-10V for VDS and 0-5V for VGS.

.NH 2 Circuit 3

The following file determines the dc transfer curve and the transient pulse response of a simple RTL inverter. The input is a pulse from 0 to 5 Volts with delay, rise, and fall times of 2ns and a pulse width of 30ns. The transient interval is 0 to 100ns, with printing to be done every nanosecond.

.NH 2 Circuit 4

The following file simulates a four-bit binary adder, using several subcircuits to describe various pieces of the overall circuit.

*** SUBCIRCUIT DEFINITIONS .SUBCKT NAND 1 2 3 4 * NODES: INPUT(2), OUTPUT, VCC Q1 9 5 1 QMOD D1CLAMP 0 1 DMOD Q2 9 5 2 QMOD D2CLAMP 0 2 DMOD RB 4 5 4K R1 4 6 1.6K Q3 6 9 8 QMOD R2 8 0 1K RC 4 7 130 Q4 7 6 10 QMOD DVBEDROP 10 3 DMOD Q5 3 8 0 QMOD .ENDS NAND

.SUBCKT ONEBIT 1 2 3 4 5 6 * NODES: INPUT(2), CARRY-IN, OUTPUT, CARRY-OUT, VCC X1 1 2 7 6 NAND X2 1 7 8 6 NAND X3 2 7 9 6 NAND X4 8 9 10 6 NAND X5 3 10 11 6 NAND X6 3 11 12 6 NAND X7 10 11 13 6 NAND X8 12 13 4 6 NAND X9 11 7 5 6 NAND .ENDS ONEBIT

.SUBCKT TWOBIT 1 2 3 4 5 6 7 8 9 * NODES: INPUT - BIT0(2) / BIT1(2), OUTPUT - BIT0 / BIT1, * CARRY-IN, CARRY-OUT, VCC X1 1 2 7 5 10 9 ONEBIT X2 3 4 10 6 8 9 ONEBIT .ENDS TWOBIT

.SUBCKT FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 * NODES: INPUT - BIT0(2) / BIT1(2) / BIT2(2) / BIT3(2), * OUTPUT-BIT0/BIT1/BIT2/BIT3, CARRY-IN, CARRY-OUT, VCC X1 1 2 3 4 9 10 13 16 15 TWOBIT X2 5 6 7 8 11 12 16 14 15 TWOBIT .ENDS FOURBIT

*** DEFINE NOMINAL CIRCUIT .MODEL DMOD D .MODEL QMOD NPN(BF=75 RB=100 CJE=1PF CJC=3PF) VCC 99 0 DC 5V VIN1A 1 0 PULSE(0 3 0 10NS 10NS 10NS 50NS) VIN1B 2 0 PULSE(0 3 0 10NS 10NS 20NS 100NS) VIN2A 3 0 PULSE(0 3 0 10NS 10NS 40NS 200NS) VIN2B 4 0 PULSE(0 3 0 10NS 10NS 80NS 400NS) VIN3A 5 0 PULSE(0 3 0 10NS 10NS 160NS 800NS) VIN3B 6 0 PULSE(0 3 0 10NS 10NS 320NS 1600NS) VIN4A 7 0 PULSE(0 3 0 10NS 10NS 640NS 3200NS) VIN4B 8 0 PULSE(0 3 0 10NS 10NS 1280NS 6400NS) X1 1 2 3 4 5 6 7 8 9 10 11 12 0 13 99 FOURBIT RBIT0 9 0 1K RBIT1 10 0 1K RBIT2 11 0 1K RBIT3 12 0 1K RCOUT 13 0 1K .PLOT TRAN V(1) V(2) V(3) V(4) V(5) V(6) V(7) V(8) .PLOT TRAN V(9) V(10) V(11) V(12) V(13) .PRINT TRAN V(1) V(2) V(3) V(4) V(5) V(6) V(7) V(8) .PRINT TRAN V(9) V(10) V(11) V(12) V(13)

*** (FOR THOSE WITH MONEY (AND MEMORY) TO BURN) .TRAN 1NS 6400NS .OPTIONS ACCT LIST NODE LIMPTS=6401 .END

.NH 2 Circuit 5

The following file simulates a transmission-line inverter. Two transmission-line elements are required since two propagation modes are excited. In the case of a coaxial line, the first line (T1) models the inner conductor with respect to the shield, and the second line (T2) models the shield with respect to the out- side world.

.NH APPENDIX C: BIPOLAR MODEL EQUATIONS

(G terms omitted) min

Acknowledgment:

This section has been contributed by Bill Bidermann at HP labs.

.NH 2 D.C. MODEL

qVB'E' qVB'C' qVB'C' qVB'C' ----- ----- ----- ----- IS NF*kT NR*kT IS NR*kT NC*kT IC = --(e - e ) - -- ( e -1) - ISC( e -1) QB BR

qVB'E' qVB'C' qVB'E' qVB'C' IS NF*kT IS NR*kT NE*kT NC*kT IB = -- (e -1) + -- (e -1) + ISE(e -1) + ISC(e -1) BF BR

NOTE: The last two terms in the expression of the base current IB represent the components due to recombination in the BE and BC space charge regions at low injection.

If IRB not specified

RB-RBM RBB' = RBM + ------ QB

If IRB specified

TAN(Z)-Z RBB' = 3(RB-RB * --------------- + RBM Z*TAN(Z)*TAN(Z)

Where:

-1+(144IB/(pi*pi*IRB)+1)**0.5 Z = ----------------------------- 24/(pi*pi)*(IB/IRB)**0.5

Q1 QB = -- (1+(1+4Q2)**0.5) 2

1 _____________

Q1 = VB'C' VB'E' 1 - ---- - ---- VAF VAR

qVB'E' qVB'C' IS ----- ------ --- NF*kT IS NR*kT Q2 = IKF (e -1) + --- (e -1) IKR

NOTE: IRB is the current where the base resistance falls halfway to its minimum value. VAF and VAR are forward and reverse Early voltages respectively. IKF and IKR determine the high current beta rolloff with IC. ISE, ISC, NE and NC determine the low current beta rolloff with IC.

.NH 2 A.C. MODEL

qVB'E' d IS NF*kT VB'E' CBE = ------- (TFF* -- (e -1)) + CJE(1- ----) - MJ d VB'E' QB VJE

Where:

VB'C' -------- 2 1.44VTF TFF = TF ( 1 + XTF * (IF/(IF+ITF)) * e )

qVB'E' ----- NF*kT IF = IS( e -1)

CB1 = CBC*(1-XCJC)

CB2 = CBC * XCJC

qVB'C' ----- qIS kT VB'C' -MJC CBC = TR ( ----- e ) + CJC (1 - ---- ) NR*kT VJC

VC'S' -MJS CSS = CJS(1 - ---- ) VJS

NOTE: all junction capacitances of the form V -M C0*(1- --- ) phi

revert to the form

M*(V-FC*phi) C0/((1-FC)**M) * (1 + ----------- ) phi(1-FC)

when V > FC*phi ( For CSS assumes FC = 0 )

.NH 2 NOISE MODEL

4kT 2 ---- IRBB' = RBB' DELTA f | | | 4kT | 2 ___ | IRC = RC DELTA f | Thermal noise | | | 4kT | KF*IB**AF 2 ---- |_________ IRE = 2REB DELTA f+ f DELTA f

Note: The first term is shot noise and the second term is flicker noise.

2 ICN = 2qIC DELTA f

Note: This is shot noise.

.NH 2 TEMPERATURE EFFECTS

All junctions have dependences identical to the diode model but all N factors are considered equal 1.

T BF and BR go as (----) XTB TNOM

when NF=1.This is done through appropriate changes in BF , BR and ISE, ISC according to the following equations respectively:

T ---- * XTB BF' (or BR') = BF (or BR) * (TNOM)

qEG T-TNOM --- ------- T (XTI-XTB) Nk T*TNOM ISE' (or ISC') = ISE (or ISC) *( ---- ) * e TNOM

.NH 2 EXCESS PHASE

This is a delay (linear phase) in the gm generator in AC analysis. It is also used in transient analysis using a Bessel polynomial approximation. Excess phase, PTF, is specified as the number of extra degrees of phase at the frequency

1 f = ----- Hertz 2piTF

.NH APPENDIX D:

.ALTER STATEMENT AND THE SOURCE-STEPPING METHOD

The .ALTER statement allows SPICE to run with altered circuit parameters.

General form:

This line introduces the element(s), device(s) and model(s) whose parameters are changed during the execution of the input file.

The analyses specified in the file will start over again with the changed parameters. The .ALTER line with the lines defining the new parameters should be placed just before the .END card.

The syntax for the element (device, model) lines is identical to that of the lines with the original parameters. There is no limit on the number of .ALTER lines and the circuit will be re-analyzed as many times as the number of .ALTER cards. Subsequent .ALTER operations employ parameters of the previous change. No topological change of the circuit is allowed.

can enhance DC convergence. But it is slower than direct use of the Newton-Raphson method. Therefore it is best used as an alternative to achieve convergence of DC operating point when the circuit fails to converge by using the Newton-Raphson method.

The source-stepping method is used by SPICE when the variable ITL6 in the .OPTIONS line is set to the iteration limit at each step of the source(s). For example,

will cause SPICE to use source-stepping method with iteration limit 30 at each step.

By default, ITL6 is 0 which means to use the Newton-Raphson method directly.